I traced the pinout of my GM ROM today just to confirm some of the conjecture in this thread, and raise a couple more questions:
https://pastebin.com/nzxFhpXg
- Pins 1-2 of the ROM socket indeed are wired to Vpp on all of the GM Flash chips.
- /WE is not only present on the GM edge, but it's properly wired to all Flash chips. Whether /WE is configured on the Pippin itself for in-system programming, I don't know.
- There are 16 8-bit Flash chips on the GM board instead of the four 16-bit PSOP chips on the retail board. Each Flash chip has 18 address lines vs. the retail board's PSOP chips which have 19. The GM board makes up for this with a 74F86 quad-XOR gate. On two of these gates, one input is tied to pin 22 (A18 on the retail board), the other input is tied to Vcc or GND, and the outputs are tied to all /CE lines on one side of the board. In effect, this splits the ROM image between the two sides of the PCB-- first half on one side, latter half on the other.
- Data lines wired to DQ0-7 on one side of the PCB are tied to the opposite lines on the other side of the PCB, i.e. a DQ0 is tied to a DQ7 of its complement chip, DQ1 to DQ6, etc. Does this mean the latter 2MB of the GM ROM have their bytes reversed?
