I'm beginning to have doubts about an underlying assumption made in these ProcSwap threads. I'm wondering if "drop in replacement" is necessarily implied by two CPUs in a series having a compatible BGA interface. A newer, faster, bigger cache CPU in a series is part of an upgrade path for existing systems, not necessarily to be implemented without specified changes to a preexisting logic board design for proper function.
In looking at implementation specs. for several G3 and G4 CPU generations I see tighter and tighter support circuitry spec'd for the "solder side" of the CPU in terms of caps for power supply and decoupling for specific sections of the CPU to reduce/filter noise within the CPU itself. That's IIRC and as far as I understand it..
You might want to take a really close look at what's implemented under your processor card to check if what you find that was required for implementation of the native CPU resembles closely enough the specs for the target CPU support system.
It also looks to me that wholesale changes in grid arrays may be following major changes in the arrangement of the support circuitry specified for down under.
Color me clueless. :huh:
It looks like in this instance it may not be too serious of an issue.
According to the white papers for both processors, Decoupling Recommendations and Connection Recommendations are identical between the 603ev and the 740.
The Pull-up Resistor Requirements show several differences between the 603ev and the 740.
The 603ev says:
"The 603ev requires high-resistive (weak: 10 KOhms) pull-up resistors on several control signals of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the 603e or other bus master. These signals are—TS, ABB, DBB, ARTRY.
In addition, the 603ev has three open-drain style outputs that require pull-up resistors (weak or stronger: 4.7 KOhms–10 KOhms) if they are used by the system. These signals are—APE, DPE, and CKSTP_OUT.
During inactive periods on the bus, the address and transfer attributes on the bus are not driven by any master and may float in the high-impedance state for relatively long periods of time. Since the 603ev must continually monitor these signals for snooping, this float condition may cause excessive power draw by the input receivers on the 603ev. It is recommended that these signals be pulled up through weak (10 KOhms) pull-up resistors or restored in some manner by the system. The snooped address and transfer attribute inputs are—A[0–31], AP[0–3], TT[0–4], TBST, TSIZ[0–2], and GBL.
The data bus input receivers are normally turned off when no read operation is in progress and do not require pull-up resistors on the data bus.
The 740 says:
"The MPC740 requires high-resistive (weak: 10 KΩ) pull-up resistors on several control signals of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the MPC740 or other bus masters. These signals are TS, ABB, DBB, and ARTRY.
In addition, the MPC740 has one open-drain style output that requires a pull-up resistors (weak or stronger: 4.7 KΩ–10 KΩ) if it is used by the system. This signal is CKSTP_OUT.
[APE & DPE are also mentioned by the 603ev]
During inactive periods on the bus, the address and transfer attributes on the bus are not driven by any master and may float in the high-impedance state for relatively long periods of time. Since the MPC740 must continually monitor these signals for snooping, this float condition may cause excessive power draw by the input receivers on the MPC740 or by other receivers in the system. It is recommended that these signals be pulled up through weak (10 KΩ) pull-up resistors or restored in some manner by the system. The snooped address and transfer attribute inputs are A[0–31], AP[0–3], TT[0–4], TBST, and GBL.
[TSIZ[0–2] are also mentioned by the 603ev]
The data bus input receivers are normally turned off when no read operation is in progress and do not require pull-up resistors on the data bus.
Other data bus receivers in the system, however, may require pullups, or that those signals be otherwise driven by the system during inactive periods. The data bus signals are DH[0–31], DL[0–31], DP[0–7].
If address or data parity is not used by the system, and the respective parity checking is disabled through HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and should be left unconnected by the system. If all parity generation is disabled through HID0, then all parity checking should also be disabled through HID0, and all parity pins may be left unconnected by the system." [This bolded section in the 740 whitepaper is not mentioned at all in the 603ev whitepaper]
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