MDU in IIci & IIsi: Same ASIC and . . .

[Trash80toHP_Mini]

. . . if they're the really the same, where did the other 63MB vacate its seat on the memory bus? :?:

I'm wondering if the 1MB limit for Bank A might be the physical implementation on the Motherboard.

Each bank of RAM is decoded into one of two fixed contiguous 64MB address spaces. Since these banks are at fixed physical locations

(see Figure 2-1), the overall RAM address space will not be

contiguous. Bank A occupies physical addresses $0000 0000 to

$03FF FFFF and Bank B occupies physical addresses $0400 0000 to

$07FF FFFF.

If true, there's apparently going to be as much headroom in the IIsi memory address map for Bank A as there is for Bank B, so I'm back to wondering about MemHackin' the IIsi again.

Bank A main logic board RAM cannot be changed in the field.

This says to me that the additional (RAS?) lines for larger capacity ICs went unimplemented on the PCB, unlike the field upgradeable 128k PCB which could be hacked up to its design spec of 512k. Given the purposely lamed design spec of the IIsi, I can see why they didn't make the same "mistake" again and warned against even trying to upgrade memory in the field. HEH! [}] ]'>

If I'm reading the DevNote correctly (given my spotty track record . . . what are the odds of that? : ) the limitation is not do to the ROM of the IIsi, just do to the MoBo's Memory Bus being lamed. So my theory is that it ought to be possible to patch the unimplemented lines from the MCU's pins, along with those implemented in support of the first Meg (or not as the case may be) to an adapter card replacing the DRAM on the MoBo.

I'm wondering if four inexpensive 32MB 72 pin SIMMs might possibly be mounted on identical adapters in Bank B's sockets. 16 bits/16MB of the 32 bit data path on each would be addressed normally as Bank B and the other half of each SIMM would be addressed as Bank A, using the missing signals patch wired from MCU.

Would it also be possible to leave the first MB of buffered RAM on the MoBo untouched by leaving the requisite patch wire solder point vias of those particular Row and Address Select lines on the adapter PCBs unimplemented? If possible, branching off the first MB (buffered for use as Video Memory) of memory physically might simplify things considerably. Since the CPU addresses the Memory bus in 32 bit chunks, will it be electrically possible to have the two "sides" of each 72 pin SIMM attached to the 30 pin SIMM connectors on the MoBo, as it looks to me as if neither side of that branched circuit's DRAM ICs can possibly be ROW and Bank selected at the same time? It's probably way better to A/B Gate select the data lines for each side than just branching them, but that's no biggie.

Dunno, Memory mappin' NOOB here unfortunately . . .

. . . so I figured I'd better ask before getting excited about any possibilities this time around. :lol:

 

[Trash80toHP_Mini]

Aha! I finished my coffee . . . Column Address Strobe and Row Address Strobe along with Bank Select. What else am I missing?

I'm very curious about the possibility of accessing the two halves of 72 pin 32/24bit Data/Address SIMMs independently on the same 30pin SIMM 16/12bit Data/Address Bus as different Banks altogether by patching the necessary bank select signals to the adapter.

 

[Trash80toHP_Mini]

Next question: I wonder if I'm making a mistake about the way a standard 72 pin SIMM is organized? Is it possible to address each side of the SIMM's data bus independently? Might I need to look at further hacking composite SIMMs at the gate aggregation level (terminology?) to achieve this?

Welcome back, trag. Did you and the family have a nice vacation? [] ]'>