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Technical explanation of why the LC, LC II, and Classic II have a 10MB RAM limit

Phipli

Well-known member
On the LC / LC II RAM limit topic ...

I was looking at the Sonnet Presto (an LC 040 PDS processor upgrade) and it mentioned that the software includes a patch to make the LC II recognise the full 12MB if you have two 4MB SIMMs installed (plus the 4MB onboard). It says not for the LC, but I don't know if that is just because it only has 2MB soldered. I'm considering soldering in the other 2MB on my LC to find out.
 

Phipli

Well-known member
That’s right. I can’t use the 8MB SIMMs in my SE/30, for instance.
Just checked the datasheet for the chips. Your SIMMs use 4Mbit X 4bit word RAM chips. This means that there is a total of 16bits on the board, but 30pin RAM is only 8bit wide. This is why a) 8MB SIMMs are weird and rare, and b) yours have a PAL. The PAL is switching things about to present the chips as 8M of 8bits. If that makes sense.

It's banking the chips as two sets of 4MByte.
 

croissantking

Well-known member
Does that mean that the PAL sits in between the chips and the memory controller, so the computer doesn't interface directly with the chips? Does that introduce any sorts of issues with timing?
 

Phipli

Well-known member
Does that mean that the PAL sits in between the chips and the memory controller, so the computer doesn't interface directly with the chips?
I suspect it decodes some of the address lines and controls the chips enable pins. It shouldn't need to get in the way of the datalines.
Does that introduce any sorts of issues with timing? Seems over-complicated.
Yes, but it is within spec or it simply wouldn't work. These are not the only SIMMs like this. I have some with many many many chips and multiple chips for decoding.
 

croissantking

Well-known member
Quite an interesting module, how does it work?

B20 looks like a network resistor. T21 looks like the PAL/GAL on my 8MB SIMM.
 

dougg3

Well-known member
I hope I'm not too late to the party on this thread! I've recently been looking into the Color Classic's ROM, in particular the tables used for setting up the MMU, and I think some of the research I've been doing might be relevant to this discussion. The Color Classic (and likely the LC II as well) have a strange physical memory map.

On most 68k Macs, the ROM is physically at something like 0x40800000. Sometimes on older machines it's even mapped to the entire range of 0x40000000 to 0x50000000. This usually leaves a ton of space starting at 0x0 for RAM. For example, the IIci seems to have everything in the physical address space from 0 to 0x3FFFFFFF (1 GB) reserved for RAM, although I suspect it's really only is capable of decoding 0 to 0x7FFFFFF (128 MB).

On the Color Classic, and I'm assuming also the LC II, the physical memory map is...weird. I think it's because of the way that some of the higher address lines don't get decoded by the Spice chip (or in the case of the LC II, the V8 chip). Since A30 doesn't get fed into the V8/Spice/Eagle, it's not even capable of differentiating between physical addresses 0x40000000 and 0x00000000, so the address map definitely had to change from how other systems like the IIci do it. The MDU in the IIci, in comparison, has access to all 32 address lines, so it doesn't have this silly limitation.

So instead, the CC's ROM is physically mapped from 0xA00000 to 0xDFFFFF, which leaves room for up to 4 MB of ROM. The CC only used 1 MB of ROM, but I think this means there is room for 3 more MB of ROM (can you say bootable 3 MB ROM disk? :cool:) The MMU in 32-bit mode gets set up so that you effectively access it at 0x40A00000, but it's really getting turned into a physical address of 0xA00000 under the hood. BTW, I think this also explains why in 32-bit mode, these models have the ROM at virtual address 0x40A00000 instead of 0x40800000 like most others.

Taking this further, the physical address space reserved for RAM is 0x0 to 0x9FFFFF -- which is 10 MB in size. Exactly matching the limitation we all know well.

I guess my overall question is: doesn't this mean the 10 MB limit has to do with the way that the V8/Spice/Eagle/etc. chipsets decode addresses? It kind of explains, in my mind anyway, why SizeMemory is limiting itself to 10 MB total. If it were possible to have more than 10 MB, where would the additional memory be mapped physically? It can't go directly after the first 10 MB, because that's where the ROM is. Is the V8/Spice capable of mapping that extra 2 MB of RAM somewhere else in the physical address space?

It does make me wonder what the Presto 040 does to allow making full use of the 12 MB. Maybe there's a hardware aspect to it as well? Since the card has access to the full set of A0-A31 address lines on its 040 CPU, maybe it does some special address decoding of its own? Or is it just patching the ROM's MMU tables? I can't figure out in my head how it would work as long as the Spice/V8/etc. chip is still involved, unless those chipsets have some crazy way to remap the extra RAM somewhere else.

The LC III is completely different. The Sonora chipset it uses is more like normal Macs where it's fully decoding the address lines so the ROM is physically mapped at 0x40800000 and there's plenty of room below that for lots of RAM.

Is my understanding here completely off base? I would love to be proven wrong!
 

David Cook

Well-known member
Comparing the block diagram in the Classic II, LC II, and Color Classic developer notes:

Classic II shows 2MB onboard RAM, and 12 bit RAM address bus (not completely accurate -- only 11 lines to the SIMM slots), and 25 (A31 + A23 to A0) CPU address lines to the V8/Spice/Eagle.

1694614576408.png

Same for the LC II, except for 4 MB onboard RAM.

1694614834983.png

However, on the Color Classic, Apple claims four additional CPU address lines going to Spice, meaning now 29 address lines (A31, A27-A0)! (Apple is also more accurate in describing the RAM address lines as being only 11).

1694615159167.png

Bomarc only shows the standard 25 CPU address lines going to Spice, not 29. Bomarc shows 11 RAM lines going to the SIMM slots. That limits SIMM memory to 8 MB, unless Spice includes a sneaky unconnected pin.

Since A30 doesn't get fed into the V8/Spice/Eagle, it's not even capable of differentiating between physical addresses 0x40000000 and 0x00000000

In all three machines, the ROM is on the main address/data bus path. It does not go through V8/Spice/Eagle. So, the MMU can map it anywhere and address it without going through V8/Spice/Eagle. Yet, V8/Spice/Eagle controls when ROM output is enabled. So, V8/Spice/Eagle needs some knowledge of when the ROM is being addressed.

It wouldn't surprise me if they originally were going to have the Color Classic mirror the LC III feature set (32-bit data bus width and maximum 36 MB memory) just like the Classic II mirrored the LC II the year before (except for video). I mean the Color Classic even switched to the slide-out motherboard with PDS slot for easy upgrades. Why not allow more memory?

16MB SIMMs were about $600 each at the time. It would have cost as much to add 32MB of memory to the Color Classic as the machine cost itself. Perhaps that's why they product management team didn't think a 10 MB limit was a big deal for a compact Mac with a 10" screen.
 

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dougg3

Well-known member
However, on the Color Classic, Apple claims four additional CPU address lines going to Spice, meaning now 29 address lines (A31, A27-A0)! (Apple is also more accurate in describing the RAM address lines as being only 11).

Bomarc only shows the standard 25 CPU address lines going to Spice, not 29. Bomarc shows 11 RAM lines going to the SIMM slots. That limits SIMM memory to 8 MB, unless Spice includes a sneaky unconnected pin.

Hi David, thanks for reading my huge wall of text! Yeah, I also noticed that in the CC dev note, and assumed it was a mistake since the Bomarc schematic only shows A0-23 and 31 going into Spice. I think it's because the A24-27 do indeed go to the PDS slot, and they mistakenly put them as going to Spice as well. I'm pretty sure the dev note is wrong about that.

In all three machines, the ROM is on the main address/data bus path. It does not go through V8/Spice/Eagle. So, the MMU can map it anywhere and address it without going through V8/Spice/Eagle. Yet, V8/Spice/Eagle controls when ROM output is enabled. So, V8/Spice/Eagle needs some knowledge of when the ROM is being addressed.

It's true that the ROM is on the main address/data path, but since (as you pointed out) V8/Spice/Eagle is in control of the ROM output enable signal, that means that V8/Spice/Eagle is indeed deciding where the ROM is mapped in physical address space. This can't be changed by the MMU. The MMU only gets to decide which virtual addresses go to which physical addresses. The physical address mapping is one of V8/Spice/Eagle's responsibilities. It's also deciding the physical addresses of other stuff like SCSI/SCC/etc by activating their enables when necessary.

I'm thinking there is going to be logic in V8/Spice/Eagle that is looking at A31 and A23-A20 to decide whether or not the ROM /OE signal should be asserted. At least in the CC, whenever A31 is 0 and A23-20 is 0xA, 0xB, 0xC, or 0xD, then the ROM /OE will be asserted. I doubt this is configurable in software...

My question is: where does V8 physically map the upper 2 MB of memory if you have 12 MB installed? If Apple did indeed add the ability to physically map it somewhere else, the MMU could be configured (only in 32-bit mode) to stitch together all 12 MB to appear like it's from 0 to 0xBFFFFF. But it would require inside knowledge of how V8 works. And I would question why Apple didn't just do it themselves in that case. Which leads me to assume it's not mapped anywhere else...although I hope I'm wrong!

16MB SIMMs were about $600 each at the time. It would have cost as much to add 32MB of memory to the Color Classic as the machine cost itself. Perhaps that's why they product management team didn't think a 10 MB limit was a big deal for a compact Mac with a 10" screen.

That sounds about right.

BTW, this discussion has led me to realize there is one advantage of the way they laid out the address space weirdly in the LC II/CC/etc.: it gives you access to 10 MB of RAM in 24-bit addressing mode as opposed to 8 MB on earlier stuff like the IIci and IIsi.
 

David Cook

Well-known member
in the LC II/CC/etc.: it gives you access to 10 MB of RAM in 24-bit addressing mode as opposed to 8 MB on earlier stuff like the IIci and IIsi.

Wait! What? Does it really? I'm going to have to try that.

If so, that's a perfect trick question for a Macintosh 68K Quiz: "How much RAM is available is 24-bit mode?"
 

Phipli

Well-known member
Wait! What? Does it really? I'm going to have to try that.

If so, that's a perfect trick question for a Macintosh 68K Quiz: "How much RAM is available is 24-bit mode?"
An SE with a Upgrade board and Compact Virtual gives you 16MB of RAM on a machine running in 24bit mode...

Now that is something I don't understand. Where did they put the memory mapped hardware?!
 

dougg3

Well-known member
Wait! What? Does it really? I'm going to have to try that.

If so, that's a perfect trick question for a Macintosh 68K Quiz: "How much RAM is available is 24-bit mode?"

I honestly haven't tested it myself, but based on the 24-bit mode address map of the LC II, CC, etc., I'd be very surprised if it didn't! Let me know if you ever test it.

An SE with a Upgrade board and Compact Virtual gives you 16MB of RAM on a machine running in 24bit mode...

Now that is something I don't understand. Where did they put the memory mapped hardware?!

Oh interesting...16 MB would be the entire available 24-bit address space with not even any room for ROM either, lol. It's probably doing some virtual memory magic and paging things in and out of a smaller chunk of 24-bit address space. That stuff is way over my head! :)
 

David Cook

Well-known member
Ha!

1694648801050.png

I don't know why System Software 7.0.1 doesn't know this is actually an LC II. I ran TattleTech to make it clear. So, you have to add the memory values together to see that more than 8MB is addressable by apps.

Regardless, yup, @dougg3 is spot on about this particular group of computers being able to address 10MB with 24-bit addressing using stock System Software.
 

Arbee

Well-known member
The LC and LC II are the same logic board with a CPU and ROM swap. In MAME, 7.0.1 says they're both an LC, but 7.1.1 correctly distinguishes them.

The Color Classic does not have extra address lines going to Spice. Here, have the real Apple schematics. :cool:
 

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