Trash80toHP_Mini
NIGHT STALKER
I've been looking into the memory subsystem of the IIsi and I noticed a glaring difference between the address lines between Bank A on the MoBo and the SIMM Slots of Bank B:
The MDU (Memory Decoding Unit) Controller ASIC sends 12 bits of addressing shared by the SIMMs in bank B, but only 8 bits for the DRAM ICs in Bank A.
My guess is that this is due to the organization of the individual DRAM ICs, their limited capacities and number of address lines. I'm hoping that the way the control signals organize and the addressing of the four pairs of DRAMs translates into addressing four 16MB SIMMs in Bank A . . .
. . . but my concern is that this might be a basic limitation on expansion of Bank A that's built into the MDU.
Comments. please?
The MDU (Memory Decoding Unit) Controller ASIC sends 12 bits of addressing shared by the SIMMs in bank B, but only 8 bits for the DRAM ICs in Bank A.
My guess is that this is due to the organization of the individual DRAM ICs, their limited capacities and number of address lines. I'm hoping that the way the control signals organize and the addressing of the four pairs of DRAMs translates into addressing four 16MB SIMMs in Bank A . . .
. . . but my concern is that this might be a basic limitation on expansion of Bank A that's built into the MDU.
Comments. please?