Golden Potato
Well-known member
On and off over the past 5 months I’ve been working on a design for a memory upgrade board which will max out my Mac 512K at 4MB of RAM. I haven’t come across any projects like this in my searches, but if it’s already been done please let me know.
I’ve made a schematic with some notes regarding my thinking, and I’d like someone else with knowledge of Macintosh memory addressing to review it as a sanity check.
I did assemble the circuit on a couple of breadboards, but it was an absolute mess, and due to some combination of poor connections, lead impedance, and potentially interference, it didn’t work.
My next step is to go straight to laying out a PCB as a prototype to do a real test. I’ve got some fairly precise measurements to take to ensure pin headers will correctly find their way into sockets installed on the logic board. But before I spend too much time on that, I would really appreciate a sanity check on the design.
Some background:
The main part of design consists of the application of two existing techniques for upgrading memory:
One part creates a new RAM address signal, RA9F, which is created by taking VID/~u and C2M as control inputs to one half of a dual 4 input multiplexer. Address lines A19 and A20 are connected as two inputs to the multiplexer. The remaining two inputs are tied high. C2M selects between A19 or A20, and if VID/~u is high (video hardware accessing memory) then the output RA9F is held high to help keep video accesses at the top of memory. This technique is how RA8F is created when upgrading from 128K to 512K, and I believe it’s similar to how a stock Mac 512K creates this RAM address signal. Outlined in a mod described here: http://dserver.macgui.com/Dr Dobbs Fatten Your Mac 1985.pdf
The other part creates additional CAS lines to select between additional RAM ICs. This is done by taking A21, ~CAS0, and ~CAS1 as inputs to a 3 to 8 demultiplexer to create ~CAS0F, ~CAS1F, ~CAS2F, and ~CAS3F. When A21 is low, ~CAS0F and ~CAS1F are controlled like they would be normally. When A21 is high, those two CAS lines are held high and ~CAS2F and ~CAS3F take their place. This is similar to a classic 1MB mod described here: https://archive.org/details/Classic_Mac_Tech_Info.PDF/page/n12/mode/1up
One concern I had was ensuring video hardware memory accesses are kept at the top of RAM. Its mentioned here that on stock 128/512K Macs there are hardware pull ups on the address lines, so that the address lines will float high during video memory cycles: https://web.archive.org/web/20230822174017/https://macgui.com/news/article.php?t=470
However, there are no hardware pull-ups for A21. I’ve checked the schematic and confirmed with a resistance check between A21 and the 5V rail.
I suppose I could just add a pull up resistor to the address line, but instead I cascaded the two main portions of the mod by utilizing the unused half of the dual 4 input multiplexer to select A21 as an input to the CAS generating demultiplexer when VID/~u is low, and forcing it high when VID/~u is high regardless of the actual state of A21. In that case the upper CAS lines (~CAS2F and ~CAS3F) are only accessible.
I could see a few ways to go about adding new memory ICs in different configurations. Either leaving the RAM address signals alone and add many more CAS lines for 256K ICs, or use 1MB ICs, or maybe SIMMs, but in the end using 4-bit DRAM ICs seemed to make sense for less ICs and hopefully less generated heat. The issue is that these ICs are not dual ported. Their output data are already buffered on the logic board, but their input data needs to be buffered, so the addition of tristate inverters suits the need.
Does anyone know if the Mac makes use of dual ported memory in a way that doing as I show in my schematic would prevent this from working?
In addition to the schematic, I attached a couple of my old notes. Some may not be relevant, but I still find it useful as those mods of which this design is based on do not provide very good schematics to explain how it works, and my notes helped me work through it.
I’ve made a schematic with some notes regarding my thinking, and I’d like someone else with knowledge of Macintosh memory addressing to review it as a sanity check.
I did assemble the circuit on a couple of breadboards, but it was an absolute mess, and due to some combination of poor connections, lead impedance, and potentially interference, it didn’t work.
My next step is to go straight to laying out a PCB as a prototype to do a real test. I’ve got some fairly precise measurements to take to ensure pin headers will correctly find their way into sockets installed on the logic board. But before I spend too much time on that, I would really appreciate a sanity check on the design.
Some background:
The main part of design consists of the application of two existing techniques for upgrading memory:
One part creates a new RAM address signal, RA9F, which is created by taking VID/~u and C2M as control inputs to one half of a dual 4 input multiplexer. Address lines A19 and A20 are connected as two inputs to the multiplexer. The remaining two inputs are tied high. C2M selects between A19 or A20, and if VID/~u is high (video hardware accessing memory) then the output RA9F is held high to help keep video accesses at the top of memory. This technique is how RA8F is created when upgrading from 128K to 512K, and I believe it’s similar to how a stock Mac 512K creates this RAM address signal. Outlined in a mod described here: http://dserver.macgui.com/Dr Dobbs Fatten Your Mac 1985.pdf
The other part creates additional CAS lines to select between additional RAM ICs. This is done by taking A21, ~CAS0, and ~CAS1 as inputs to a 3 to 8 demultiplexer to create ~CAS0F, ~CAS1F, ~CAS2F, and ~CAS3F. When A21 is low, ~CAS0F and ~CAS1F are controlled like they would be normally. When A21 is high, those two CAS lines are held high and ~CAS2F and ~CAS3F take their place. This is similar to a classic 1MB mod described here: https://archive.org/details/Classic_Mac_Tech_Info.PDF/page/n12/mode/1up
One concern I had was ensuring video hardware memory accesses are kept at the top of RAM. Its mentioned here that on stock 128/512K Macs there are hardware pull ups on the address lines, so that the address lines will float high during video memory cycles: https://web.archive.org/web/20230822174017/https://macgui.com/news/article.php?t=470
However, there are no hardware pull-ups for A21. I’ve checked the schematic and confirmed with a resistance check between A21 and the 5V rail.
I suppose I could just add a pull up resistor to the address line, but instead I cascaded the two main portions of the mod by utilizing the unused half of the dual 4 input multiplexer to select A21 as an input to the CAS generating demultiplexer when VID/~u is low, and forcing it high when VID/~u is high regardless of the actual state of A21. In that case the upper CAS lines (~CAS2F and ~CAS3F) are only accessible.
I could see a few ways to go about adding new memory ICs in different configurations. Either leaving the RAM address signals alone and add many more CAS lines for 256K ICs, or use 1MB ICs, or maybe SIMMs, but in the end using 4-bit DRAM ICs seemed to make sense for less ICs and hopefully less generated heat. The issue is that these ICs are not dual ported. Their output data are already buffered on the logic board, but their input data needs to be buffered, so the addition of tristate inverters suits the need.
Does anyone know if the Mac makes use of dual ported memory in a way that doing as I show in my schematic would prevent this from working?
In addition to the schematic, I attached a couple of my old notes. Some may not be relevant, but I still find it useful as those mods of which this design is based on do not provide very good schematics to explain how it works, and my notes helped me work through it.
