Register-register operations have a straightforward implementation, but then there are instructions that perform some reading or writing of memory, actually most do this since it's CISC. There are also branch instructions which require a more complex implementation.
Now when accessing memory, there is this concept of different "targets" of the access depending on the address. Some accesses are to be conducted over the 68000 bus. Others may involve reading from or writing to arrays in the memory of the STM32H7/SDRAM. In order to categorize these accesses, we need a tree structure.
In order to traverse the tree structure, we divide the 24-bit address into three 8-bit pieces, the high, middle, and low bytes. The high and middle bytes are used as indices into the doubly-indirect tree. What's found there is a structure containing four function pointers (total of 16 bytes). Each structure basically tells how to access the given 256-byte region of the 68000's address space. The function pointers go to routines for loading, storing, and executing code from the given region of memory.
So to execute a load or store operation (possibly in the course of executing a more complicated, CISC-y instruction), compute the target address, then use that to go into the tree structure. Then branch-and-link to the routine implementing the load/store. That routine can look in an array, use the qSPI interface to talk on the bus, whatever.
To execute a branch instruction, compute the target address, use it to go into the tree structure, then branch to the routine for executing instructions in that area of memory. That's where the "basic steps required to execute an instruction" I gave in the post before last should be implemented.
Actually that procedure for executing an instruction only applies to instructions stored in main RAM, which is cached in the Maccelerator's SDRAM. A slightly different procedure should be implemented for executing code from something which is not cached (e.g. a peripheral card with a ROM).
