Good Catch! Linking that schematic was worth it!Agreed, that’s a great sign that it should work for this project!
Thanks for sharing this. I saw a blurb in the schematic in the linked GitHub repository talking about using an AND gate to control the ~OE line to the RAM ICs based on either the upper or lower ~CAS lines being asserted rather than just tying ~OE low like I had originally. The purpose for this allowing the use of EDO type RAM if FPM type becomes unavailable.
One more criterion to add to the list for the schematic redraw!
I have to say, I find the way you use chat very enjoyable, like a kind of log of the thoughts, reflections, and decisions you make for the development of your project; it's much better than the stickers on the corkboard, isn't it?