Memory Addressing Questions

[Trash80toHP_Mini]

I've been looking into the memory subsystem of the IIsi and I noticed a glaring difference between the address lines between Bank A on the MoBo and the SIMM Slots of Bank B:

The MDU (Memory Decoding Unit) Controller ASIC sends 12 bits of addressing shared by the SIMMs in bank B, but only 8 bits for the DRAM ICs in Bank A.

My guess is that this is due to the organization of the individual DRAM ICs, their limited capacities and number of address lines. I'm hoping that the way the control signals organize and the addressing of the four pairs of DRAMs translates into addressing four 16MB SIMMs in Bank A . . .

. . . but my concern is that this might be a basic limitation on expansion of Bank A that's built into the MDU.

Comments. please?

 

[bear]

8 bits is all that's needed to address the fixed 1 MB of memory in bank A, arranged as it is using 256k x 4 chips.

2^(8 row addresses + 8 column addresses + 4 bits) * 8 chips == 8 megabits == 1 megabyte.

Why bother routing more lines that are just going to force you to allocate more gates for buffers and multiplexers, add to the capacitive load, and take up valuable PCB space, while serving no useful purpose whatsoever?

 

[Trash80toHP_Mini]

I know it can address 4MB of RAM in Bank A, uni did that upgrade.

I'm looking into adapting four, double banked 32MB 72-pin SIMMs to the SIMM slots in Bank B. One bank of each to be addressed normally as Bank B, filled with four 16MB SIMMs and the other Bank addressed as Bank A and stuffed with the same. Mobo DRAM and Video Cnnector to be removed, so there's no attempted buffering of DRAM as Vampire VRAM.

It's a stupid Mac trick, why else would I be trying to do it? :lol:

 

[uniserver]

I am wondering if this 16 megs of ram AI is sending me is going to work… in the IIsi

8 chips

2megs per chip.

 

[uniserver]

also:

i just ran 7.5.5 on my mac II

its only got 4 megs of ram installed. just like the onboard ram of the IIsi.

for some odd reason it would only allow me up to 12 megs of Virtual memory.

where it seemed like the IIsi would let me make the paging file as big as i wanted. 50mb +

The hard drive that is in the mac II is a 700mb quantum, not a 73 gig hd like what i have in the IIsi.

the boot partition in the IIsi was still only 1.7 gb.

I am aware the MacII is only a 68020.

 

[unity]

Ya, you need a card. The FPU I think? I don't recall, its been so long since I played with a IIsi. But pretty sure it needs an FPU or something to be able to set it higher. Then again, I could be wrong!

 

[uniserver]

lol i just remembered that its dirty and needs mode32 anyways.

or does it? i should install mode32 and see what happens.

too bad its on a 1.44 disk… humm. floppy emu to the rescue.

 

[unity]

lol i just remembered that its dirty and needs mode32 anyways.
or does it? i should install mode32 and see what happens.

too bad its on a 1.44 disk… humm. floppy emu to the rescue.

Hmmm... maybe that is what you need. I can't recall! All I remember is that I did not have much love for the IIsi, the two we had in the lab among a few Iici and many 6100/66!

 

[uniserver]

I installed mode32 and toggled 32bit mode. rebooted and then i was able to select as much VM as I wanted, With the Mac II.

 

[unity]

I installed mode32 and toggled 32bit mode. rebooted and then i was able to select as much VM as I wanted, With the Mac II.

Ah! Good to know. Now I will forget into another 10 years.

 

[bear]

You need 9 address bits to get 4 MB in bank A. It's either already there, or uni put it there.

Four "double-banked" 72-pin SIMMs somehow wired as two banks per SIMM makes 8 banks. Don't forget a bank of 30-pin SIMMs is 4 modules because each is 8 bits wide, and you need 4 together to get the 32 bits that will fill the data bus. One 72-pin SIMM is already 32 bits wide.

 

[Trash80toHP_Mini]

Yep, using the control lines I can access just the necessary sections of each 72-pin SIMM needed to output the 8bits of needed to make the 32bit word in each access far Banks A & B . . .

. . . figuring out how the Data and Addressing is multiplexed(?) in the four 74ALS275 3-State Bus Transceivers should be a big help . . .

. . . or a major hindrance! ;D

It looks like I need to reflect the Control, Data and Address lines of Bank A back onto the bus for Bank B and find or synthesize a Bank Select in order to make this work. I'm hoping I can manage to do that on the two n.c. pins of the 30-pin SIMMs/Slots, dunno, we'll see. Worst case scenario for that appears to be the need to put a circuit on a PCB somewhere between MDU and Bank A to make a gate circuit on my 30-pin to 72-pin adapters work as planned.

Gotta love playing with a 20-33MHz memory bus! :

This thread was a false alarm, I forgot about the SE/30 and IIci using MDU for full A & B SIMM bankage. All the lines are there, with just resistor packs between them and the Bank B SIMMs/Bank A DRAM ICs.

The killer is that I don't really have any need to do this hack, the Rocket, its onboard memory banks and its Fast SCSI II storage subsystem will be the main CPU and I/O in the SuperIIsi under RocketShare. This hack is really just for fun!

 

[uniserver]

its already there… i didn't do anything other then change the chips.

i am hoping there is going to be enough to address these 2m chips to give me 16 megs onboard!\

well on here with the IIsi and AI's Q605 as well!

 

[Trash80toHP_Mini]

Do your higher capacity DRAMs have the same pinout as the stock ICs?

 

[uniserver]

Yes they do. the new 2m chips have the same pinout as the oem chips. MinerAI found them.

It would be really awesome if they work…

but to be honest, If they don't work for what ever reasons. (in the IIsi)

Hey, i'm happy with 4mb's in the IIsi, at-least that works.

 

[CC_333]

but to be honest, If they don't work for what ever reasons. (in the IIsi)Hey, i'm happy with 4mb's in the IIsi, at-least that works.

Yeah, and since that's the minimum for a small System 7.1.x install, that's pretty spiffy.
And it's four more megabytes more for the total (built-in plus a full bank of SIMMs).

c

 

[Trash80toHP_Mini]

A couple of patch wires and resistors might just do the trick if it doesn't work out o inside the box. [}] ]'>

 

[Trash80toHP_Mini]

It's late, I'm tired and visions of Block Diagrams and Schematics are dancing around in my head. |)

I checked out the 74ALS245 function and it looks to be the video buffering mechanism. I neglected to mention that the 8 address bits were not a subset of the address bits heading to the Simms in Bank B. They originate from entirely different pins on MDU. I'm guessing the IIci and IIsi use those eight separate address bits for the buffered DRAM as Vampire VRAM setup in both machines.

If there's a Video Card in the IIsi running the monitor and nothing hooked up to the DA-19 connector on the MoBo at startup, then Bank A is never buffered by the 245s from the main memory bus. Bank A would appear to be contiguous with Bank B and its twelve dedicated addressing lines running from different pins on MDU in Bank A's unbuffered state.

Looks to me like you might have a shot at getting al's 16MB of DRAM ICs to work in Bank A if you aren't using that dratted Vampire Video kluge, uni.

Then again . . . :

 

[Trash80toHP_Mini]

Head-desk-head-desk-head-desk . . . :I

OOPSIE!!!! When I was up late last night I misread the schematic for the IIsi and never actually counted the lines.

I just put red lines emanating from the proper legs of the MDU in my AI file, counted them to cross-check . . . and came up with too many!

TEN address lines and the W/E line were what I counted for a total of eleven. Took a gmuch closer look at the schematic again and realized it said "A0-A9" NOT "A0-A7" so much of my concern just vanished.

You may have enough address lines for al's bigchips to work in Bank A of the IIsi, uni!