What's going on on the Outbound SE docking card?

[cheesestraws]

I was lucky enough to get hold of the Outbound Laptop docking card for the Macintosh SE. This card allows the Outbound Laptop to drive the zombified ROMless SE like a giant PDS card and use all its I/O. The card consists of a single programmable logic device and an enormous quantity of 74 series logic, nearly all of which are inverters and flipflops.




In this thread, I'm going to try to work out how it works, both for my own curiosity and also to reverse-engineer the pinout between it and the laptop, so I can use it. Stuff will get added to this thread as I have the energy and concentration to do it. Please do not expect speed.

Let's start with the data lines.

The treatment of each data line available on the SE PDS slot (D0..D15) is the same. Each data line has two latches, each with a three-state output. One latch has its output facing the data bus, one has its output away from it. Each of these latches attaches to a pin on JP2, the wider connector at the bottom of the photo above. This allows the Laptop to put 16 bits onto the bus by clocking a bit into one of the latches then enabling its output, or to temporarily latch a value off the bus by clocking a bit into the other latch, then when it is ready to have that bit appear on the pin on JP2, it can enable the output of that latch. A schematic for a single data line is thus:



(the inverter is there because the output of the '534 is inverting, so the data needs to be inverted on the way in).

What about the address lines?

The address lines are similar, but unidirectional: the Laptop can set the address lines on the SE LB, but nothing on the SE LB can contorol the address bus as far as the Laptop is concerned. The address lines are multiplexed onto the same 16 pins on LP2. Observant readers will note that there are more than 16 address lines: there are two banks of address lines.



So, the laptop multiplexes all the address and data lines onto these 16 pins. How the latches are clocked and enabled is the next thing to work out, I think.

 

[demik]

Very interesting, thanks. Si there is only one PAL in all of this ?

 

[cheesestraws]

Yup. One PAL and a positive sea of 74 series flipflops.

I've got the PAL equations (thanks to @Bolle), but since the PAL mostly seems to be controlling the clocks and output enables on the flipflops, I thought it best to understand what the flipflops were doing first!

 

[eharmon]

Oh that's wild, I never knew this existed. Can it even drive the display?

 

[cheesestraws]

Oh that's wild, I never knew this existed. Can it even drive the display?

Yup! Bonkers, isn't it.

 

[cheesestraws]

A little more spelunking this evening. Here is which flip-flop chips are used for what bus lines. I'm hereby adopting the Acorn convention of host and parasite: in this case, the host being the SE and the parasite being the laptop.



Some notes:

1. The chips marked in pink, which allow the parasite to write to the host's data bus, have their OE and clock pins tied together, unsurprisingly.
2. The chips marked in turquoise, which allow the host to write to the parasite's data bus, have their OE and latch enable pins tied together, but not tied to the OE and clock of any of the other sets (again, unsurprisingly).
3. The chips marked in green are about 2/3 of the address bus, in some order that I'm sure made sense to someone. These have their clock inputs and output enables tied together (the latter along with the below).
4. The chip marked in yellow contains the rest of the address bus, and the chip marked in pink I haven't traced out yet. The yellow, green and pink chips all have a common output enable, and the clocks of yellow and pink are tied together.

So we have the following signals that immediately need explaining:

• D0..16, parasite to host, output enable and clock
• D0..16, host to parasite, output enable and latch enable
• A1.11, 19-23, clock
• A12..18 and ???, clock
• Address bus in general, output enable

These don't immediately seem to come from the PAL, they seem to wander off into discrete logic. Next bit to dig into there.

 

[demik]

Nice writing.

Is there any control/interrupt lines somewhere ?

 

[cheesestraws]

There must be - trying to work out where they are is one of the things I need to do! But even the OE signals don't come straight off the PAL, they come out of a random NAND gate somewhere. There is much mapping yet to do...