I don't know about $100. A circuit board is going to cost $10 - $20 in quantities of 200. The PDS connector will be about $5 - $7. A Xilinx FPGA to do most of the heavy lifting will run around $15 - $20. Some memory to use as GRAM (Graphics RAM) will be another $5 - $20 (uncertainty there because of sooooo many price/performance trade-offs). DACs will run another $5 - $15 (uncertainty because I haven't researched DACs much). Then miscellaneous connectors for video out (support for external monitor), that back of the CRT connector (is that still available?) and cable harness plugs and receptacles will probably add another $20. Then add in miscellaneous components such as a few PLDs to sort out some of the PDS addressing and caps and resistors and such for another $5 - $10.Grayscale video for the SE/30 though is more true to the definition of "rare" than most other items I've seen on EBAY.
Now won't one of you out there just build us a $100 copy of the video board and grayscale card and drivers so we can all enjoy grayscale?!
So you get a minimum *Parts* cost of $65 and a high end of $112 per unit. And that's just for parts. No assembly or reimbursement for skull sweat and development. And there will be costs for development, such as an FPGA development kit for $100 - $200. Some custom circuit boards to interface the FPGA development board to the PDS slot and some more circuit boards for prototypes. Each set of test/prototype circuit boards will cost about $200.
So material costs for development will easily reach $1000. And the material costs in the first paragraph are for 100 or 200 units, so one is looking at investing $6500 - $22,400 up front for materials before selling a unit.
I'm not sure one could even make it pay with those numbers. The problem is that there may not even be 100 people willing to pay $100 per upgrade.
When I built and sold 16 MB SIMMs for the IIFX, I was able to sell 28 sets before the price dropped below $50 per set of four SIMMs. Are there four to eight times as many folks interested in upgrades for the SE/30 as there are for the IIfx?
You could cut some of the costs from my estimate a little, because I've assumed a fairly powerful FPGA to allow very fast work and gates available for hardware based Quickdraw acceleration. And I've assumed 4 - 8 MB of GRAM so that a large external monitor can be supported in millions of colors as well as the internal grayscale at 256 shades.
But those two components are not that huge a percentage of the cost and they can't be shrunk tremendously (see FPGA I/O pin discussion below). Other parts are necessities and simply cannot be discarded. One must have a PDS connector and connectors to the CRT yoke and for the external monitor and cable harness connectors.
The PLDs to help with the addressing are not strictly necessary; that work can easily be done inside the FPGA. Here's the problem. Once you get beyond about 150 I/O pins on an FPGA the only package available is BGA. I can't solder BGAs at home and paying someone else to do so in small quantities is very expensive. So we're limited to about 150 I/O pins (that's a 208 pin total package) for the FPGA.
There are around 96 or 97 relevant pins on the PDS slot. Thirty-two of which are addressing pins and another thirty-two of which are data pins. You can cut out several of the addressing pins by letting a PLD handle the high order addressing bits. Your video card is only being addressed for one value of some number of the high order bits, so a PLD can watch those address bits for the value and signal accordingly.
Then there are some number of pins needed to output the data to the digital to analog (DAC) converters which signal the CRT(s). This number could range from 24 pins (full parallel output of all color data) to three pins (serial output of each color separately). With a fast FPGA and fast GRAM, this can probably be kept to three pins. Or four pins when you add the output to the grayscale adapter.
There may be other digital output pins needed to drive the CRT, but I'm not that well educated yet.
Then you need an interface to the GRAM which could use as many as 23 address pins (8 megabytes) plus 24 or 32 data pins.
So you've got 90 (PDS) + 4 (DAC) + 23 + 24 I/O pins needed on the FPGA which is about 140 I/O pins. Plus there are probably a few more needed for the display output that I just don't know about yet. Oh and we didn't allow anything for WE, CE, OE or RS on the GRAM, nor for an interface to a firmware container (EEPROM or Flash).
I don't know how Micron managed with 100 pins on their Exceed chip. IIRC it has only 100 pins on the main chip. On the other hand there are quite a few PLDs on the board. Also, one could use a combined data bus for both the PDS slot and the GRAM and use muxes with enable signals to avoid signal interference. But that has problems if your memory bus clock speed is much different from your PDS bus clock speed (16 MHz.).
Okay, I've wandered off of cost and am just babbling about design trade offs and issues. I'd be happy to read any additions or comments.
