I got some more data on this IIcx. I'm troubleshooting this highlighted part of the circuit, and measuring voltages at the seven points marked in red. D6 is the "turn off" signal that will enable transistor Q3 to actively turn off the computer.
Here's what I'm seeing when I press and hold the power switch:
A lot of this doesn't make sense to me. C10 rises at 5V rises, as it should, but it's always about 0.9V lower than the 5V supply even once it plateaus. It should be the same voltage. I can't explain that.
UL2 pin 1 is the active low shutdown signal from the VIA chip, connected to the asynchronous clear input of the flip-flop. It's low the whole time, meaning the VIA is trying to shut off the computer. This is wrong.
UL2 pin 3 is the clock input to the flip-flop, its job is to shut down the computer if you press, release, and press the power button a second time. The way it's wired it's basically an inverter for the voltage on C15. When the power button is held in, then C15 is grounded, so the inverter output should be high and UL2 pin 3 should be as high as the power supply can make it. This looks like it's working correctly.
UL2 pin 5 is the output of the flip-flop. In a normally working computer, this should be high (as high as the power supply can make it) until you choose to shut down from the Finder menu. But in this case because the VIA is unexpectedly driving the asynchronous clear low, the flip-flop output should be low. So this is "right", but because it has wrong inputs, it ought to be wrong.
UK2 pin 5 is the output of the RS latch (the cross-coupled NAND gates). The latch's set input is active low and is at UK2 pin 1, the voltage on C10. The latch's reset input is active low and is at UK2 pin 9, the output of the flip-flop. In a normally working computer, C10 holds the set input low for a moment during startup to force the latch value to 1. The reset input remains 1 until the flip-flop is triggered. When the latch's output is 1, then the NAND output feeding D6 will be 0, transistor Q3 won't be enabled, and the shutdown behavior won't be activated. So for correct operation here UK2 pin 5 should be high (as high as the 5V supply can make it).
But that's not what happens. Aside from a little glitch on the first cycle, UK2 pin 5 remains low the whole time.
There's something about this whole circuit that I don't understand. All these 10 and 47 uF capacitors are there to provide some predictable initial voltages for the startup circuit - particularly C10 which sets the RS latch and asserts the flip-flop's asynchronous preset for a few moments after power-up. But to do this job, C10 must charge up more slowly than the 5V supply rail itself, with its big 470 uF capacitor. I believe this is the reason for the existence of R26: it slows the rate of charging on C10. Somehow that's not happening though, and C10 charges up almost as quickly as the 5V rail itself. That means the initial set and preset signals are deactivated before the 5V supply has even reached its full voltage. Something definitely seems wrong there, either the 5V supply is rising slower than expected or C10 is rising faster than expected.
Hmm... the time constant for the RC circuit composed of C10 and R26 should be R times C, 47 uF * 15K ohms = 0.705 seconds for the capacitor to reach 63.2% of its final value. But it seems to be rising from 0 to its final value in about 10-20 ms. So maybe C10 is bad?
TLDNR - This method of analysis was less useful than I'd hoped. It maybe points towards a problem with C10, possibly also a problem with the VIA, but I'm still looking at "recap the board and then try again", which is where I started.
