I'm traveling for a couple days, so I apologize for the infrequency of my posts.
The test is loading the loop count, then issuing a DMA NOP command to load the count and read it back. Since the DMA is a NOP, there should have been no bytes DMA'd, so the count should be the same. The DACK/ and/or ACKO/ lines of the 53C96 will decrement the count. These aren't 68040 signals, so I'm going to guess they go to the memory controller.
The part I'm still hung up on is it's supposedly the high byte of the 2 byte count. Since it increments by 5, and none of the expected values reported by the error code are multiples of 5, this makes some sense. At least it indicates to me I'm not confusing the LSB and MSB failure codes. The 0x03 test case is a FIFO reset error, and doesn't have the expected/actual value codes, so I don't think I'm off by one on the test code.
The count is also loaded 8bits at a time, so it shouldn't even be a problem with the higher data lines. It's using the same data lines to load both the high and low bytes.
So, if it is a DACK/ or ACKO/ signal problem, I'm at a loss as to why it seems to only be happening when the count gets fairly high.