It shouldn't be too hard to recreate...
Unfortunately, I do not have time to work on it myself. I'd be happy to consult for anyone who is working on it.
The stuff about Single Banked SIMMs in the Q605 is *wrong*. Let's start there.
Yes, it is true, that if you want to use a 64MB SIMM in the Q605, it must be single banked.
However, it is not true that all SIMMs used in the Q605 must be single banked. All of the 32MB SIMMs which we use are double bank, for example. Also, it is impossible to build a 128MB 72 pin SIMM which is not double banked. In other words, all 128 MB SIMMs are double banked, and they work in the Q605 too.
Okay, in order to have two banks on a single SIMM, the computer must run two or more independently controllable RAS lines to the SIMM socket. When the computer wishes to access one bank, it uses one of the RAS lines with the row address. When it wishes to address the other bank, it uses the other RAS line. The wiring in the SIMM socket and on the SIMM is such that one RAS line connects to the memory chips for one bank, and the other RAS line connects to the memory chips on the SIMM for the other bank.
All the other lines such as address and data are shared. However, I"m not sure about the CAS lines. Those can get a little wacky. Generally, as far as I can tell, they're only used to specifiy bytes within in a SIMM operation. In other words, they're wired so that they can be used to activate 1, 2, 3 or 4 bytes out of the 4 bytes available on a 72 pin SIMM during a given operation. Of course, if only two CAS lines are availble, then they're wired for 2 or 4 bytes. CAS lines are one-hot, not binary encoded. So two lines gives you two possibilities, not four.
You can learn a fair bit by getting the pinout of the 72 pin SIMM (available on line with some searching), and then using an ohmmeter to trace how the sockets are connected in something lilke a Q650 where there are four slots. You should find that the address and data lines are all shared amongst sockets. I'm pretty sure that each socket has two RAS lines all to itself and all the CAS lines may be shared or independent. I can't remember.
That's what you need to achieve on the Q605. The trick will be figuring out which pins are the unused RAS (and maybe CAS) on MEMCjr. However, even that isn't too hard with some guess work usually. Very tedious, but not hard.
Usually the pinout on Apple's chips of this ilk are very orderly. Get out the old ohmmeter and a magnifier if you have old eyes like me. Count how many pins the MEMCjr. has and find the dimple or cut corner or whatever that indicates pin 1. Now write 1 through however many pins on a sheet or sheets of paper.
Now, connect one probe of your ohmmeter to ground somewhere on the board (power supply connector is good) and go around the chip with the other probe. Each time you find a ground pin, label that pin's number as GND on your list. Now repeat for 5V.
This will eliminate about half the pins on the thing right off and start to establish some pattern. Like every fifth pin is connected to Pwr and another every fifth to GND or something close to that.
Now using your pinout listing for the 72 pin SIMM socket, put one probe on an address pin. Run the other probe gently and slowly over the pins on the MEMCjr, until you find the corresponding pin. Label it on your sheet. Move to the next address pin and repeat. This time it is easier because the address pins will probably be pretty close together and in order. Repeat for the CAS and RAS pins. The data pins may not run through the MEMCjr. They may run either directly to the CPU bus, or through some buffer chips and then to the CPU bus. In any event, the data pins are not very interesting anyway.
Get the pinout of the memory chips soldered to the board used to make up the 4 MB of on-board RAM. Repeat the above steps for their address and RAS and CAS pins. Oh, and you'll need to find Write Enable for both of the above as well.
The address pins should be the same (although fewer of them).
RAS should be different. This is where you'll find out if CAS is shared.
You may also wish to complete your pinout of the MEMCjr. by tracing its connections back to the 68040 CPU socket. Pull the 68040 from the socket so you can have access to the pin connections. Get the pinout of the 68040 from Freescale's website and figure out which pins on the MEMCjr. connect to the address bus on the 68040. Etc.
When you have a fairly complete pinout for the MEMCjr. it will probably be pretty obvious which pins could be the missing/available RAS lines. From there it is just mechanical aptitude work to install additional SIMM sockets.
The above method is how I established my pinouts for things like the Bandit chip in PCI Macs, and the ROM DIMM in the Beige G3 and PCI Macs, etc.
