The onboard video will always come from the onboard RAM (if there is any), so it will always use the "slower" RAM.
The Q605/LC/P475/476 has separate video RAM SIMMs, so the onboard system RAM is not used for video. Most likely your interleaving information is the relevant fact in this case.
i just realized the 4 megs of ram onboard….
they are EIGHT 512k 20pin chips.
Anything that I have that is more then 512k per chip goes to a 24 pin chip…
even the 2 extra 16meg 30pin simms i have.
Remember that the Quadras need 32 bit wide memory. So your eight memory chips must be 4 bits wide each, in order to supply 32 bits per read or write operation.
If the capacity of the chips is 512KB each (4 MB divided by eight chips) then each chip must have 1024K addresses. Or another way to look at it is that a 512KB chips is the same as a 4Mb(it) chip, and if it provides four bits at a time, then it must be 1M (1024K) X 4 bits.
1M of address space is 20 bits of addressing. Operations with RAM memory are performed with multiplexed addresses, in which the address bits are split into Row and Column segments. So, this memory is likely to be 10 X 10 X 4 bits. 10 row address bits, by 10 column address bits by 4 data bits. Although it could be 11 X 9 or some such.
So let's do a pin count. Each chip has 4 data bits, (at least) 10 address bits, and RAS, CAS and WE control lines. Additionally, there must be at least one GND and one Vcc line per chip. I think there might be an OE_ pin as well. That's 20 pins per chip.
You want a larger capacity RAM chip in the same 20 pin package, but it simply isn't possible. Any RAM chip you can use must have the same 4 data bits/pins, the same RAS, CAS, WE and OE control lines. At least one GND and VCC line. That only leaves 10 pins out of the twenty. Ten address pins gives you 10 row + 10 column address bits maximum, which is what you already have.
In order to have a larger capacity memory chip, you must add address lines, which pushes you over 20 pins.
I found an auction for a 16MB 30-pin simm, read the part number off the Siemens chips on it, did a little googling, and found
this auction for just the chips themselves ($2 each in lots of 25).
Unfortunately, the chips in that auction are 4M X 1 chips. Eight of them will only provide 8 bits of parallel data, because each of the chips is only providing one bit of data per operation. Those will not work, as Uniserver discovered. He would need to use 4M X 4 chips in order to increase the capacity, but 4M X 4 chips will be 24 or 22 pins. I'm sorry I didn't read this thread sooner. I would have liked to save you the expense.
Were the onboard chips 80ns and the chips on your SIMM 60ns? Would something like that explain the speed boost?
Probably not. In most cases, the memory controller is programmed (or built) to supply the RAS address, supply the CAS address, and then sample the data lines (or report the transaction complete to the CPU so it can sample the data bus), at a fixed time based on how many cycles the specified RAM can be expected to need to supply (or consume, for writes) the data. So, a computer which needs at least 80 ns RAM will always wait the amount of time in the specification for 80 ns RAM, before assuming that the data is available. If you install faster RAM, the data will appear on the bus sooner, but the memory controller won't know to complete the transaction earlier.
I suppose there could be calibrating memory controllers out there, which would perform a memory performance test at start up to determine what the timing margins are for the RAM, but this would be dangerous, because temperature is likely to affect the timing margins, and so 80 ns RAM might perform like 60 ns RAM at start up, and then slow down to the 80 ns specification when heated. The memory controller doesn't have any way to read the label, nor to know what the temperature is.
Modern RAM, which someone used as an example is a completely different animal. DDR2 memory for example, supplies a DQS signal along with every 4 or 8 bits of data signal. When the DQS signal arrives the memory controller knows that valid read data has also arrived. Similarly in the other direction. The FPM memory used by these old computers has no protocol to signal when the data is really on the bus. This is part of what being non-synchronous means.
That would be interesting. The Q605 definitely does at least up to 260 MB of RAM. I know that from experience. And the 4MB on board can probably be replaced with 64MB, so I imagine that machine could go to 256 + 64 = 320MB at a minimum, perhaps more.
The IIsi should go to 128MB. My understanding is that it's essentially a IIci with a microphone jack, so the memory pins should be there for 128MB.
this was from here:
viewtopic.php?f=9&t=15958
The 260 MB Q605 configuration was accomplished with a 72 pin to two 72 pin SIMM doubler, and no, the lid would not close. But it was a proof of concept, not a configuration intended for operation. The two 72 pin SIMMs were the 128 MB SIMMs we are all familiar with.
well…. 512megs of ram in a q605 would knock MinerAI's socks off.
the couple that with the 42mhz beastly OC…. man…
Don't know if this is possible. There are a couple of issues. First, how much the memory map in the ROM will allow and other ROM issues. Rob is your man for that stuff.
Second, we know that the main SIMM socket will handle a pair of 128MB SIMMs. I don't know how it does that for certain, but I believe that it (the Q605) must have the ability to control each of the RAS lines in the 72 pin socket (four total) separately.
A 72 pin SIMM bank is limited to 64MB in capacity. That is a hard theoretical limit. Explanation later.
So, the SIMM socket in the Q605 appears to be able to manage 4 banks. How many banks can the circuitry for the soldered RAM manage? It should be able to manage at least one bank of 64 MB (if you add the two address lines), but how many independent RAS lines are present or available? Or are there unused RAS pins on the memory controller chip?
Why a 72 pin SIMM is limited to 64MB per bank:
The 72 pin SIMM specification includes 12 address lines. The address lines are used twice in each memory operation (first one Row address, signaled by the RAS_ control signal, and second one Column address, signaled by the CAS_ control signal).
Twelve addresses times two equals 24 address bits. Twenty-four bits of address gives 2^24 addresses = 16M addresses (slightly more than 16 million).
The 72 pin SIMM is four bytes (32 bits) wide. So every address points at 4 bytes. So, 16M addresses, each pointing at 4 bytes of data, gives 16M X 4 = 64M bytes of capacity.
Banks Later DIMMs have additional address pins labeled "bank" pins but there was no such thing on 72 pin SIMMs. Instead, 72 pin SIMMs have four RAS_ control signals/pins. For a single bank SIMM, only two of the RAS_ lines may be tied together and routed to the RAS_ pins on the memory chips.
However, if one wants a two bank SIMM, then two of the RAS_ lines are tied together and routed to one bank of memory chips, and the other pair of RAS_ lines are tied together and routed to the other bank of memory chips. The RAS signal is always the first control signal associated with any operation, so arranging the SIMM so that a bank of memory chips only gets a RAS signal when it is being used works great as a Bank selection signal.
Of course, the computer using the multi-banked SIMMs must have circuitry/firmware which allows it to control its RAS_ signals one or two or four at a time and understand that doing so addresses separate banks of RAM. So the computer and the SIMM both must agree about how the RAS signals will be used to indicate banks. A really flexible computer can run tests at startup to determine whether a SIMM has more than one bank of memory chips on-board. Such flexibility is probably rare.
From what I've read, the 72 pin standard does not envision the RAS_ lines being used individually, only in pairs, so I'm still puzzled how a pair of 128MB SIMMs worked in a SIMM doubler, but perhaps Apple went off spec. and allowed the RAS to operate independently. Additionally, I could not get 128MB SIMMs to work in the PM6100 even though it supports 64MB SIMMs and two bank SIMMs, suggesting that something is wonky with how Apple associates RAS lines. So there's still some lack in my knowledge about exactly how finely the RAS_ signals can be mixed and matched.
If any of you have a copy of the 72 pin SIMM JEDEC standard kicking around and wants to email it to me, feel free.
JFYI, with the 610 series, you can't interleave RAM SIMMs because of the way they arranged the banks. It has half the SIMM slots, and rather than just leaving off the top 2 SIMMs, they've split things up so every other bank will be empty, preventing any interleaving of the SIMM slots. 8mb soldered is still interleaved, but the SIMM slots are gimped.
Given that the address and data lines are probably common amongst the SIMM sockets, could one just switch which RAS pin is ocnnected to one of the SIMM sockets on the 610 and get interleaving back? If Apple used the same chip set for the 610 as they did for the 650/800, then the pin(s) that control the complementary SIMM sockets are still present, just unused. It should be a relatively minor operation to lift the pin or cut the trace for the existing RAS (and maybe CAS?) signal and run a rework wire from the memory controller's complementary RAS line to the SIMM socket to turn the socket into one which is capable of interleaving with the unmodified socket.
If I ever get the 610 logic board out of the attic again....
yeah that would be pretty bad-ass to epoxy a 72pin simm slot to the bottom of the PCB and run some wires
but not through the rom slot holes.
I think that I've read of a Japanese fellow doing something like this to the Q605. Pulling up the soldered down RAM and adding a SIMM socket via wires to the board. It would be messy.
What about the Q630/LC580?
The 630 can take up to a 128mb SIMM in a 32x32 configuration, I believe. The second simm slot, on boards that have it, can only take up to 64mb (I think you need to use the 128mb SIMM, and only 64 of that is visible). There's several threads about it, and trag has described the SIMMs to use. It should be the same 128mb simms that work in the 605.
Yes, the part of the Apple Dev, Note which claims that the Q630 will not address 64M SIMMs lies. From what I can gather, the first SIMM socket has two banks available and the second SIMM socket (if present) has only one bank of control available. So the maximum is 64M X 3 (two banks in original SIMM and 1 bank in optional SIMM) plus on-board RAM. It should be possible to expand the on-board to 64MB as well, yielding 256 MB of RAM, but again, that would be messy with wire everywhere, or funny custom circuit boards in the SIMM sockets.
If you got this far and thought it was useful or were bored to tears, please say something. Often, when I post these data dumps they're met with echoing silence. I don't know whether that's because they're not very useful and too long, etc. or because folks just don't feel like there's much left to say afterwards.
