There's a fine old tradition of increasing memory capacity by piggybacking chips on each others backs like that. What the image doesn't show at first glance, is that it is not just a matter of soldering all the pins together, one to one. One must also get the additional higher address pin and apply some digital magic to some of the control lines to make it work. If you just piggyback directly, you simply have two chips trying to do identical work. They need a way of knowing that one set is used when an address pin that they can't see (not enough address pins) is '0' and the other is used when that address pin is '1'.
That said, it greatly reduces the amount of extra wiring, because most of the address pins, and all of the data pins are shared.
However, on the gripping hand, figuring out which control signals to modify can be a bear. You can't just hook up OE_ because that only handles reads. You can't assume that you can just modify RAS_ because the machine might use CAS before RAS refreshes, and that would mess with those. Without knowing the basics of how the machine is accessing RAM for both refresh and read/write operations, it gets tricky. I think that if you modify OE_ and WE_ both, then it should always work, but I'm not 100% certain about that.