lameboyadvance
Well-known member
With throughhole ICs like that he would have been better off making a custom PCB with PCB push pins for the IC holes connecting to a SIMM socket.
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Q605/LC475 (onboard) ram upgrade.
- Thread starter uniserver
- Start date
Trash80toHP_Mini
NIGHT STALKER
Those are two different projects, either of which were probably prototypes done as proof of concept and determination of the traces needed for such a PCB. I'll be dong something very similar to the bottom one for each of my adapters for Bank B before worrying about actual PCBs. Such prototypes are effectively antenna farms, filling the entire case with nasty RFI or the whole room with the lid off. [}
] ]'>
I've got pics of the prototype and final PCB in another, similar project. I'll dig 'em up to post here. The pic of the 72-pin SIMM with red wires attached might be from a similar project, dunno I'll see when i dig up the pics a/o bookmark.
Meanwhile, the block diagram above shows more of what I'm aiming to do in the Memory Addressing Questions thread . . .
found 'em! ;D
adapt_simm_16k.jpg[/attachment]
http://www.zxprojects.com/index.php/simm-adapter-for-replacing-lower-memory
This is an adaptation of good ole' DIP memory to a 30-pin SIMM, but it illustrates the process nicely. Bank A on the Q605/LC475 may be as badly lamed as on the IIsi and the DRAM on all these systems is SMT anyway. So this process would be fruitless at Bank A's location in the IIsi. So that's why I'm working on moving Bank A to a super-set of Bank B at that location for my project and suggesting an under the board PCB maximification adaptation project for the Q605/LC475that ought to work for the Q630 as well.
] ]'>I've got pics of the prototype and final PCB in another, similar project. I'll dig 'em up to post here. The pic of the 72-pin SIMM with red wires attached might be from a similar project, dunno I'll see when i dig up the pics a/o bookmark.
Meanwhile, the block diagram above shows more of what I'm aiming to do in the Memory Addressing Questions thread . . .
found 'em! ;D
adapt_simm_16k.jpg[/attachment]
http://www.zxprojects.com/index.php/simm-adapter-for-replacing-lower-memory
This is an adaptation of good ole' DIP memory to a 30-pin SIMM, but it illustrates the process nicely. Bank A on the Q605/LC475 may be as badly lamed as on the IIsi and the DRAM on all these systems is SMT anyway. So this process would be fruitless at Bank A's location in the IIsi. So that's why I'm working on moving Bank A to a super-set of Bank B at that location for my project and suggesting an under the board PCB maximification adaptation project for the Q605/LC475that ought to work for the Q630 as well.
Trash80toHP_Mini
NIGHT STALKER
The only stupid question is the one that doesn't get asked.
Bank A and Bank B each have their own sets of address lines coming from adjacent pins on MDU in the IIsi/IIci and SE/30. Dunno how MEMCjr(?) is set up in the Q605/LC475. I don't have that schematic, but my guess would be that it's the same kind of deal. Buzz the connections to see if the MDU setup translates to the later Quadra Memory Controller.
You could almost certainly hotwire the additional address lines from the equivalent of MDU to Bank A. Figure out the rat's nest of control and addressing lines to run to a stack high enough of compatible pin count DRAM ICs on the existing pads on the MoBo in order to max out the memory config. But it would be one horribly fugly kluge mechanically, electrically, appearance wise, in terms of RFI transmission and one bear of a process to actually implement such a cluster-whatever. Even that still leaves you a SIMM slot short of maxing out the memory configuration overall.
I'm not crazy enough to take on that project, so it's a PCB adaptation under the board or nothing as far as I'm concerned.
Doubling onboard memory by cribbing the pin assignments from a sixteen compatible chip, double sided SIMM could be a doable double-stuffer hack. Has anyone got a SIMM like that to buzz the connections?
Bank A and Bank B each have their own sets of address lines coming from adjacent pins on MDU in the IIsi/IIci and SE/30. Dunno how MEMCjr(?) is set up in the Q605/LC475. I don't have that schematic, but my guess would be that it's the same kind of deal. Buzz the connections to see if the MDU setup translates to the later Quadra Memory Controller.
You could almost certainly hotwire the additional address lines from the equivalent of MDU to Bank A. Figure out the rat's nest of control and addressing lines to run to a stack high enough of compatible pin count DRAM ICs on the existing pads on the MoBo in order to max out the memory config. But it would be one horribly fugly kluge mechanically, electrically, appearance wise, in terms of RFI transmission and one bear of a process to actually implement such a cluster-whatever. Even that still leaves you a SIMM slot short of maxing out the memory configuration overall.
I'm not crazy enough to take on that project, so it's a PCB adaptation under the board or nothing as far as I'm concerned.
Doubling onboard memory by cribbing the pin assignments from a sixteen compatible chip, double sided SIMM could be a doable double-stuffer hack. Has anyone got a SIMM like that to buzz the connections?
