The only stupid question is the one that doesn't get asked.
Bank A and Bank B each have their own sets of address lines coming from adjacent pins on MDU in the IIsi/IIci and SE/30. Dunno how MEMCjr(?) is set up in the Q605/LC475. I don't have that schematic, but my guess would be that it's the same kind of deal. Buzz the connections to see if the MDU setup translates to the later Quadra Memory Controller.
You could almost certainly hotwire the additional address lines from the equivalent of MDU to Bank A. Figure out the rat's nest of control and addressing lines to run to a stack high enough of compatible pin count DRAM ICs on the existing pads on the MoBo in order to max out the memory config. But it would be one horribly fugly kluge mechanically, electrically, appearance wise, in terms of RFI transmission and one bear of a process to actually implement such a cluster-whatever. Even that still leaves you a SIMM slot short of maxing out the memory configuration overall.
I'm not crazy
enough to take on that project, so it's a PCB adaptation
under the board or nothing as far as I'm concerned.
Doubling onboard memory by cribbing the pin assignments from a sixteen compatible chip, double sided SIMM could be a doable double-stuffer hack. Has anyone got a SIMM like that to buzz the connections?