techknight
Well-known member
Nope. I need the AN994/D.
Closest I come was a post in the Freescale forum, but the attachment is long gone.
Scavenging around with that search, I found an amiga 68020 accelerator, and its associated PAL code in a document from the 80s. This document also refers to that same application note, which is how it hit on the search engine.
Problem is, I dont understand CUPL so i dont know how to convert CUPL into discrete logic.
But from what I gather so far, attaching a 68020 to the system bus, might as well go with 030, little difference. Seems relatively streight foward.
Just have to have the logic to break it down to 16 bit cycles, and then you need the Syncronous generation logic becuase its missing in the 020. Basically the E, VPA, etc.. signals.
Then the bus mastering logic.
As long as we have these 3 logic blocks, everything else pretty much just works. The Amiga they were converting the 7Mhz bus signal to the async 16Mhz so the guy had to create a whole bunch of extra logic to keep DSACK happy, and other things happy. Whereas in my case, the bus is already at 16Mhz, and I will keep the same for the CPU. So i can cut out that extra logic.
Closest I come was a post in the Freescale forum, but the attachment is long gone.
Scavenging around with that search, I found an amiga 68020 accelerator, and its associated PAL code in a document from the 80s. This document also refers to that same application note, which is how it hit on the search engine.
Problem is, I dont understand CUPL so i dont know how to convert CUPL into discrete logic.
But from what I gather so far, attaching a 68020 to the system bus, might as well go with 030, little difference. Seems relatively streight foward.
Just have to have the logic to break it down to 16 bit cycles, and then you need the Syncronous generation logic becuase its missing in the 020. Basically the E, VPA, etc.. signals.
Then the bus mastering logic.
As long as we have these 3 logic blocks, everything else pretty much just works. The Amiga they were converting the 7Mhz bus signal to the async 16Mhz so the guy had to create a whole bunch of extra logic to keep DSACK happy, and other things happy. Whereas in my case, the bus is already at 16Mhz, and I will keep the same for the CPU. So i can cut out that extra logic.
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