SE/30 Xceed greyscale adapter cloning thread

Found an interesting thread wally started in 2007:



Precursor to your neck board build ten years later, my friend:



It'll be a fun ride trying to get a revamped 603-48 hooked up to that harness and neck board.

This is a known issue:





My instinct says we are having a disk space issue, but I don't have admin access to the server itself to check or remedy the issues.

As to why cross-posted images work, my guess is because those are already uploaded to the site.

I've notified wthww but, well, there's only so many hours and he's got a job and has been away from his desk recently as well, so I'm not surprised by the lag time.

EDIT:

Tagging @Trash80toHP_Mini for clarity.

Still can't upload an image error-200



Dunno what the three GRID Signals are as yet, but all head from the A/B on the J3 connector to J5 on the GS Neck Board. Can't make heads or tails out of the Color30 Harness Schematic, so I combined its pinout data with the loopy harness illustration with its spatial relationship viewpoint.  Illustration's all kinds of wonky as documented in a picture of a warped page at an angle.I guess you can't have everything, LOL! So I cleaned up in terms of which wire plugs more exactly where according to the schematic. Proofreading would be much appreciated.

Looks to me like the Color30 GS section is riding the MoBo's HSYNC as well as VSYNC mentioned in the docs. It passes the signals straight over to J2 on the AB.

Maverick may not need more than VSYNC as mentioned, but it pulls in and passes on HSYNC as well.

_____________________________________________________________________________________

Video Timing Generator:

Video timing signals are generated by counting through a series of mode
registers associated with the vertical and horizontal video waveforms. Please
refer to the attached drawing for a pictorial description of the timing elements.
The horizontal state machine cycles through each element twice per line to
allow for equalization pulse generation.

Most of the timing elements will be self-explanatory to those familiar with video
timing signals; however, there are some timing elements that are unique to the
Maverick design. The FS1 period is used to fill any pipeline that may exist
between the VRAM and the DAC. The FS2 period is used to empty the pipeline.
NS defines the period where bus access to the DAC will not interfere with the
generation of video. HS22 is used for the generation of equalization pulses
only.

Interlaced and noninterlaced video formats are supported. Vertical state
transitions may be made at half-line or whole- line boundaries. Equalization
pulses in the vertical blanking signal may be enabled or disabled. Display
sizes up to 2K x 2K are supported. Vertical sync and field ID may be generated
externally or internally. For external vertical sync Maverick will wait for an
external sync pulse at each vertical front porch period. The falling edge of the
active low external sync will force the vertical timing state machine to go into the
internal vertical sync state. NTSC timing waveforms are generated by putting
the video timing in interlaced mode, selecting the proper horizontal and vertical
resolutions, using half line counts in the vertical state machine, and turning on
the equalization pulses.

_____________________________________________________________________________________

Gut call (Ludicrous WAG) is that much of the 306-48 schematic will need to be excised and adapted for VSYNC and HSYNC driving the timings. I wonder if the 306-GS clone (or the Color30) really needs an oscillator while operating in GS mode? Every clock in the book is available for reference on the PDS with VSYNC and HSYNC available on the MoBo's A/B connector. Video goes straight through to the A/B unmolested and exits the other side where it's picked up by the Color30 for passing on to the Neck Board when in external monitor detected mode.

Dunno, I just make pretty pictures. []

Cory5412 said:

My instinct says we are having a disk space issue, but I don't have admin access to the server itself to check or remedy the issues.

As to why cross-posted images work, my guess is because those are already uploaded to the site.

Click to expand...

Thanks, I hadn't seen that thread pop up with recent entries. FWIW, it's only been the last week or so that I've been affected. Appreciate all you guys do very much and not complaining. Just reporting informally at the scene of the crime, as it were for specific examples. iFrog image showed up really nicely in the reply window as did all the other workarounds. Hit submit and the images revert to links in the forum and in the edit window. Strange stuff. Thanks again.

Trash80toHP_Mini said:

Probably wrong, but sounds to me like the card is using the SE/30 internal video's sync pulse as the primary input for timings?

Click to expand...

In internal GS mode the VSNC signal coming from the logicboard is fed into Maverick. The video statemachine is synced to that signal.

Maverick will still get a pixel clock signal from the clock generator that matches the resolution and framerate. HSYNC for internal GS mode is generated by a separate counter GAL which is clocked by the pixel clock.

In non-GS mode with an external display connected the incoming logicboard HSYNC is just passed through by one of the GALs.

HRMMM, so you're saying it runs from the clock generator and only syncs up with MoBo's VSYNC output? What's the pixel clock rate, don't recall offhand? I figured it's in whatever Hz, looped down from the 16MHz System Clock as it must be for MoBo Video?

Since we're not cloning Maverick and its clock generator, we've gotta figure out how to pull the crystal cans for 640x480 output off the 306-48 schematic and substitute something for Compact Res. GS timings. Those can be generated from PDS clocks, no?

What the heck are the three GRID lines? Looks like something the A/B cooks up from VIDEO, VSYNC and HSYNC inputs that's needed to run any Neck Board, The GS Neck Board uses 'em right off the shelf in either mode.

Whatever, not thinking straight, too tired from AI playtime today. Spotted a booboo and went back to fix it, then I added the GRID lines and whited out all extraneous information for the JPG. My harness illustration is 100% complete, for signal lines, less all power and ground lines for crystal clarity.i



If we follow the Color30 Harness model as is, we'll be set up for phase whatever when the time comes for adding video out of some sort.

Trash80toHP_Mini said:

What the heck are the three GRID lines?

Click to expand...

They supply a voltage to each of the three grids inside the tube for things like brightness, focus and cutoff. Those go straight through from the A/B and carry a high voltage (up to ~500V on one of them AFAIR)

So they're only CRT power basics, unrelated to the three inputs from MoBo to J5 or via Xceed board handoff when that's installed?

Just had a silly notion, but thought I'd float it anyway. Every SE/30 VidCard I've seen is in the maximum or close to the maximum expansion SE/30 card form factor in Apple's specs. Having a board even close to that size sitting atop an accelerator/adapter or one of your low profile adapters on top of an Asante NIC defeats the purpose of putting a clear case on an SE/30. Was thinking that implementing the 603-48 based Color30 doppelganger within the form factor of the socketed PowerCache might be worth looking into. The GS harness could be hard wired to the VidCard or on a thinner, horizontal plug. Either way, you'd feed the harness up through the rectangular opening of the chassis during installation of the MoBo/Socketed GS VidCard. Haven't looked at it yet, but there might be room on an edge to put PDS connector thruholes allowing standard installation for those who have the Socketed PowerCache. might score one in the future or don't wish to have a stock board modified?

A Socketed GS card also gets around that pesky 2 TTL line driving limitation of PDS buffering, which might allow for a three expansion card setup by having the third on the floor?

Either way, you'd obviously have to have a 68030 Socket on board, which can be used as a small footprint PDS interface. [}]

Trash80toHP_Mini said:

pesky 2 TTL line driving limitation of PDS buffering

Click to expand...

Not sure where you got that from, but the PDS on the SE/30 is not buffered. It's the raw CPU signals that go to the slot.

Also slot interrupts and that kind of stuff is not present at the CPU socket so it really only is useful for CPU upgrades or expansions that don't use the slot manager.

And not to mention it would limit the usability of the card to only those with socketed CPU's, right? 

It's in the 030 PDS slot specifications in DCaDftMF. The lines on the IIsi/SE/30 PDS are spec'd as being able to drive only two TTL inputs by Apple. Remember we went through that in ProtoCache development? Adding buffering to better support three cards and accelerator was something you thought would add too much latency as I recall?

Here it is, it's about the line driving limitations of PDS signals.  But you got me on the buffering bit, properly designed cards need to provide it right above the PDS connector.

DCaDftMF3e-1992 p.323

Some of the expansion connector signals are specified to drive one 74LS input (a
standard 74LS input load is 20 JlA high, 0.2 rnA low); other signals can drive two 74LS
inputs. These strict limitations are imposed to protect the noise and timing margins of
the main logic board. All signals needed by an expansion card should be buffered at the
expansion connector. The use of newer logic families with very low input loading allows
you more margin and flexibility in your expansion card designs.

We've got far newer logic families available for 030 PDS projects today.

Bolle said:

Also slot interrupts and that kind of stuff is not present at the CPU socket so it really only is useful for CPU upgrades or expansions that don't use the slot manager. 

Click to expand...

I didn't put in the bit about using a PDS Cap/Terminator type setup to pull those signals from the PDS on a cable to a socketed version. Any required signals could be hotwired from the solder side of any connector in a stack of PDS cards or a header on any new Accelerator adapter design to support both 030 and the 040 card you mentioned on a side note. []

pcamen said:

And not to mention it would limit the usability of the card to only those with socketed CPU's, right? 

Click to expand...

Nope, you missed a bit of my post: there might be room on an edge to put PDS connector thruholes allowing standard installation for those who have the Socketed PowerCache. might score one in the future or don't wish to have a stock board modified?

So everything about the notion depends upon the limits of the form factor, if it can't have provision for a standard, if funky lookin' PDS card, it's not really worth pursuing. A cable connector adjacent to the EuroDIN120 thruholes could pull the required signals off that PDS feed or RA headers could be installed at each pin location for breadboard jumpers or the like. If that's not electrically feasible that dead ends th notion as well.

Note that right up front I did say it was a silly notion that I'd had this morning. :lol:

That particular graphics card may not have an ASIC as in a single chip, but it might as well be just as complex. 

Sadly, in the photos, I see multiple registered PAL/GAL devices which basically form up an ASIC in a logical sense. They would have to be decapped/reverse engineered unless you study timing diagrams and can build new logic based off of that... Not easy IMHO. 

They serve a pretty powerful purpose, such as refreshing the RAM as needed (Not sure if its dual port VRAM or standard DRAM, i have seen both used). As well as controlling DTACK to insert wait states if the memory is single-port, doing a read cycle via the rasterization timing circuit, while the CPU is trying to read/write the RAM at the same time. So DRAM access requests are interleaved between the CPU and the RAMDAC. 

Its easy to probe and brute force combinational PALs back into logic verilog code, I have done this many many times. 

But registered devices, Nope.... 

Hello all,  I have a thought: would it be possible to base this project off of another SE/30 video Card?  Myself have have several of them, including a RasterOps 264/SE30, a RasterOps ClearVue GS30,  and my newest addition straight from eBay, an Interware VDR-2a.   Would it be possible to somehow split the signal coming off of the output of the video so that it could run both the internal monitor and an external one?

Here's a project that I'm sure some of you have seen that got me thinking about some possibilities:  http://spritesmods.com/?art=macsearm&page=5

@Bolle- I have a dumb question:  I have a Diimo 030 acclerator, and stacked on top of that a VDR-2a video card.  If the PDS on the SE/30 uses the raw signals coming from the onboard 16mhz 68030, what happens when you have an accelerator attached to it?  Does it still allow the stock 16mhz clock to pass through it?

Also, don't know if this helps, but someone in Japan is seller the Xceed greyscale harness:

https://buyee.jp/item/yahoo/auction/j600329379

If anybody is interested, I will happily post high resolution scans of all of the cards that I've just mentioned.  Who knows....maybe it might spark some more ideas!

And I freely admit that at the end of the day, I'm not much more than a basic bench tech...and not really a good one!

techknight said:

Sadly, in the photos, I see multiple registered PAL/GAL devices

Click to expand...

The equations for all of them are available, no reverse engineering needed. (if we are talking about the Micron 306 cards)

JT737 said:

If the PDS on the SE/30 uses the raw signals coming from the onboard 16mhz 68030, what happens when you have an accelerator attached to it?

Click to expand...

All CPU signals will be coming from the latches and buffers on the accelerator.

Clock signals and other logicboard signals that are not related to the processor itself will still come from the logicboard.

Actually having an accelerator does help with multiple cards as at least data and address lines are buffered on (most) accelerators.

Oh I didnt know the equasions were available. 

So there is nothing stopping anyone from cloning this card then basically. 

Lack of schematic in the "open source/confidential documentation" is the only problem at present, which will be fixed when a 306-48 wends its way onto Bolle's bench. Once that's done, as I understand it, it's a question of:

1) tweaking the 640x480 DA-15 external video output of the 306-48 to match internal resolution. in the formulas/clocks/electronics present.

2) modify the card to use  internal video VSYNC output as the trigger to keep the clone output in step with the A/B

At present the only visual documentation of the process I know of is the baseline function simplification of the Color30 harness I slapped together to illustrate those interconnections.



The video lines from the system board to A/B and from A/B j3 to the clone can be ignored as the consensus appears to be that Internal GS only would be the initial target of the cloning project. So the Color30's intermal/external A-B switching/passthru isn't a requirement.

Ok, the PDS as far as I am aware has no video signals present. 

However, the entire video circuit is sync with the motherboard clock signals, so you can use the clock signal present on the PDS slot as the timing source for both HSYNC and VSYNC. 

As far as reverse engineering the PCB back into a schematic, thats easy. and its non-destructive. 

I have been on a 68K project this year (not mac) that I reverse engineered 4 boards back into schematics. 

I can lend my 306-48 for this project.  @Bolle @techknight who is going to do it (who do I send it to).  I know Bolle is in Germany (right) but rumor has it he wants my broken SE/30 board anyways.  @techknight are you in the US?