Looking for Formac ProMedia 40 ROM Rip

[Phipli]

I was successful in reducing the speed of the card by editing the PCI registers.
Method:
1. enable IO-register access
"SBC 04 07"-> from 06 ... the last bit enables the IO-register access

2. enable the clock modification
"SBI 3c4 08"
"SBI 3c5 06"

3. change the SR11 register
"SBI 3c4 11"
"SBI 3c5 39" -> from 41

4. activate the change
"SBI 3c4 15"
"SBI 3c5 20"
"SBI 3c5 00"

I get less than half the speed (42 Ktris/s instead of 192 Ktris/s) in Sneek3View when rendering "25pix Grouraud tris"
The command sometimes does not get through correctly or something is not correct and the 3c4 value is 50 or 55 instead of 10 or 15.
In that case i simply send 0 to 3c4 to reset the register. This will work usually.

To write a byte to any IO-register, you can use SBI xxxxxxxx xx (Set Byte I/O-Address)
To read a byte from any I/O-address: DBI xxxxxxxx xx (Display Byte I/O-Address)

PeekPCI is quite lenient and accepts sbi and SBI as well as 000003C4 and 3c4 for the address or 08 or 8 for the data-byte.

The defaut value of SR10 is 0x24
The defaut value of SR11 is 0x41

Which would result in M: 65, N: 4, R: 1
This seems to be a strange value since it would result in 80MHz?!

M: 57, N: 4, R: 1 is much slower than the original values (4 times slower!)

EDIT: i just realized, that i was modifying SR 10 instead of SR11


EDIT2: Changing SR 11 from 41 to 56 did not change the speed in any conceivable way but it did lock up the computer after a minute or so, (corrupting the screen a bit in the process).

View attachment 98842


-Jonas

Good work.

There was an oddity I saw in the code in ROM - it toggled a different bit in the SR15 register to enable the clock to the one I expect from the documentation. The ROM seemed to toggle bit 1 instead of bit 0? Is that of interest?

 

[stynx]

Good work.

There was an oddity I saw in the code in ROM - it toggled a different bit in the SR15 register to enable the clock to the one I expect from the documentation. The ROM seemed to toggle bit 1 instead of bit 0? Is that of interest?

Maybe?
I was using infos from PC-related overclocking of the Virge. Bits-und-Bolts used 0x20 for SR15 instead of 0x01 for whatever reason...
I am a bit surprised that the boot value seems to be 0x24for SR10 and 0x41 for SR11 which would result in 40Mhz instead of 60...

 

[stynx]

Values for the 1.2.6 Rom:
SR10: 45
SR11: 7F
... something strange is going on here ...

 

[Phipli]

I am a bit surprised that the boot value seems to be 0x24for SR10 and 0x41 for SR11 which would result in 40Mhz instead of 60...

They start in a safe mode until the driver loads. It makes sense. If you're doing manufacturer trouble shooting or development it means holding shift gets the to the desktop without pushing the chip or VRAM.

40MHz makes sense for that.

Bits-und-Bolts used 0x20 for SR15 instead of 0x01 for whatever reason...

There was two ways of doing it listed in the Virge datasheet, I'll have to go back for a look after work.

 

[Phipli]

4. activate the change
"SBI 3c4 15"
"SBI 3c5 20"
"SBI 3c5 00"

Why 20? Is that because MSB?

Wouldn't that impact 15 too? Aren't the options in the manual to toggle bit 0, or to toggle bit 5?

 

[Phipli]

0x20 is the 6th bit, so the manual is saying bit 0 and bit 5, but the real world examples we're seeing are using bit 1 and 6...

So I guess I'm not counting them the right way. Does this weird counting also impact SR10 and SR11?

 

[stynx]

I used rom 1.2.6 for this test. The change of SR10 from 45 to 24 and SR11 from 7F to 41 did improve the throughput of texturized pixels from 3.5mpix/s to 4.5Mpix/s
SR15 did have the value 0x80 so i used 81 and 80 to enable the new frequency. opening the control panel did not change the frequency at all.

All you really have to do is enable the IO-registers (bit 0 of control reg. 0x04)
And then change the SR10, SR11 and SR15 values
Bit 0 of SR 15 must be set to 1 and the 0 to enable the new frequency.

 

[stynx]

Rom 1.2.6 default: 3.5 MTex/s (SR10: 45, SR11: 7F)
Rom 1.0.6 default: 4.5 MTex/s (SR10: 24, SR11: 41)

The best result that i got were with SR10: 23, SR11: 42

This got me a throughput of >5.6 MTex/s and >22Mpix/s.
>5.6MTex/s is with Z-buffer, perspective and bilinear filtering.
>22Mpix/s is untextured, Gouraud shading.

The chip gets very hot, almost too hot to touch. A heatsink is needed.

Opening the control panel and changing the resolution does not change this setting.

Did not work SR10: 23, SR11: 44 (lockup)