Anyone up for some IIcx troubleshooting assistance? We have clocks but no activity...

[Sideburn]

What I am seeing now is if I hold halt low and power up, status goes high. I let go and status goes low and stays low even when I pull halt low again.

 

[Sideburn]

But I know I was getting status to go high earlier when pulling halt low

 

[GRudolf94]

Ok, that seems to be somewhat working, but take a look at this too:

 

[GRudolf94]

I think what we're seeing is a functional CPU suffering from a measurement error.

 

[Sideburn]

If I power up and then pull halt low, status stays low. If I keep halt low and press reset then status goes high. That’s what I’m seeing now consistently.

 

[GRudolf94]

"The processor also halts if it receives a bus error or address error during the vector table read operations or the prefetch for the first instruction after an external reset. STATUS remains asserted until the processor is reset."

 

[GRudolf94]

If it dies right at the gate STATUS will always be low, unless you reset it already halted, in which case it never prefetches the first instruction, never takes that first bus fault, and never halts with STATUS low, instead starting halted with STATUS high.

 

[Sideburn]

"The processor also halts if it receives a bus error or address error during the vector table read operations or the prefetch for the first instruction after an external reset. STATUS remains asserted until the processor is reset."

Ok yeah so the cpu seems to be “not dead” hah

 

[Sideburn]

That’s what happens to status when I push reset.

 

[Sideburn]

Here’s a longer sample.

 

[GRudolf94]

Doesn't seem dead, no. At least we know it's trying to fetch from memory. Would be good to see captures upon reset of the first few address lines, and maybe a couple few datalines too. We have to establish what is causing it to fail to fetch from the reset vector

 

[Sideburn]

And that pulse happens when I let go of the reset button.

 

[Sideburn]

Doesn't seem dead, no. At least we know it's trying to fetch from memory. Would be good to see captures upon reset of the first few address lines, and maybe a couple few datalines too. We have to establish what is causing it to fail to fetch from the reset vector

Ha I may have to drag the logic analyzer out.
I need some way to clip onto the pins.

My current options are janky….

 

[Sideburn]

I suppose I can clip to the address lines somewhere else. I may have a clip that will grab onto the FPU

 

[GRudolf94]

They don't need to be all correlated, but eh that works. I've used a PLCC socket upside down to stab the logic analyzer micrograbbers onto stuff before heh

 

[Sideburn]

Ok I say we keep going

I need to go do some work work for a bit. But I’ll look into see what I’ve got to in order to clip onto the address lines and maybe hook the logic analyzer up.

 

[GRudolf94]

's aight. I gotta sort food soon anyway

 

[Phipli]

Ha I may have to drag the logic analyzer out.
I need some way to clip onto the pins.

My current options are janky….

The ROM sockets. Clip onto ROM chip pins, or plug a turned pin male header (small pins that don't bend the contacts) into the empty sockets.

 

[Sideburn]

The ROM sockets. Clip onto ROM chip pins, or plug a turned pin male header (small pins that don't bend the contacts) into the empty sockets.

Right. That’ll work. I have clips.

 

[Sideburn]

I’ll continuity check from 030 to rom and hook up to address lines. Anything else? I have 16 inputs