Oh, I built a proof of concept kind of clone thing a long time ago already but haven't pursued it any further because availability of those Xilinx chips and the clock generator IC they used for the pixel clock is meh...if we leave out the VGA video interface. @Bolle already published the JEDEC files for the Vandal Extreme, which seems to be a clone of the Gemini Ultra/Integra.
From here, the main hurdles are reverse-engineering the schematics from the PCB and dumping the configuration PROM to figure out exactly how the Xilinx XC2018 handles host bus management. @Phiply mentioned that dumping that PROM should be possible.

Indeed, that's what it does. Not sure why they choose to do that instead of properly driving the bus with actual bus drivers.it is highly likely that the Xilinx XC2018 simply replaced the 74646 transceivers and their control logic


