Here are a few steps I almost always take every time I encounter 'Sad Mac' error codes with this expansion board.
The fact that you are getting a clean and good chime strongly suggests that the power supply and some of the complementary address multiplexing logic of the expansion board are functioning correctly. This logic involves address multiplexed signals MSRA0F and MSRA1F handled by U9 and U10. It seems these components are performing as expected, and the signals tapped from the LB (Logic Board) are likely sound.
MSRA8F and MSRA9F are not involved in the address interleaving with the sound hardware, so you have to discard faulty connections between J8 and U4F (from the backside of the LB to the connections on top of the socket J8).
If J8/U4F connections are sound, your problem may mostly reside with the data bus or the control signals that route to the RAM ICs.
With the schematics on hand and the RAM expansion board installed, start by checking the resistance of each data bit trace.
Measure the resistance between the corresponding pins of the CPU (D0 through D15) and the pins of the input buffers (ICs U7 and U8). You should see values that are near-zero.
Next, check the resistance between the common buffered data bits between the relocated output buffers U20 and U21 (which must be logically traced from the backside of the LB to discard any faulty connection between the sockets on the LB and the pin headers of the expansion board) to the input buffers U7 and U8. I am referring to signals DQ0-DQ15.
If at this point everything still checks out, check the multiplexed address lines that go directly from the LB (RA2, RA3, RA4, RA5, RA6, RA7 at RP2 and RP3 pins from the backside of the LB) to the corresponding pins at the RAM ICs (RA2F, RA3F, RA4F, RA5F, RA6F, and RA7F) to ensure they are showing 47 ohms each.
Also, check RA0 from the LB to pin 4 at U9 and pin 7 at U10. Similarly, check RA1 from the LB to pin 7 at U11 and pin 12 at U9.
Finally, you could use an oscilloscope to quickly verify that you have active C2M (the 2 MHz clock at pins 4 and 10 of U1), RAS, and system WE signals on the expansion board. The System CAS signals must be present on the expansion board because the configuration you described with the Dip switches (disabling expansion RAM and enabling system RAM) works.
You can check the new generated CAS lines at test points TP1, TP2, TP3, and TP4, and the RAS and WE (RAM R/WF at R33 on the LB) signals on pins 13 and 14 on both RAM ICs.
Good luck!
Last edited:
