it's like with each successive Quadra/Centris iteration, they kept consolidating chips into new ICs
the SCC IC is present in the Wombat, as well as Quadra 700, IIci, and I'm not sure how far back
Nice work!It interprets the bits and nicely prints a little more info.
all of the stuff it prints is read from the registers or reported by the OS, the "ideal for XX mhz" takes the number of cycles in the register and basically reverses the calculation described in the ROM comments (+/- rounding errors)so is all of this "digestible" text direct output from the djMEMC? even the parenthetical comments? e.g. "(ideal for 32 ish MHz)"
Check what version of the MC88916DW is installed.
Gotcha. Well that will definitely be something to check against during the refined testing process."ideal for XX mhz" takes the number of cycles in the register and basically reverses the calculation described in the ROM comments (+/- rounding errors)
This is the one on the OE Centris 650 board where I'm testing:
I have a hunch of what this means, but can you shed some light, @trag ?The MC88916 Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for CISC microprocessor or single processor RISC systems. The RST_IN/RST_OUT(LOCK) pins provide a processor reset function designed specifically for the MC68/EC/LC030/040 microprocessor family. The 88916 comes in two speed grades: 70 and 80MHz. These frequencies correspond to the 2X_Q maximum output frequency. The two grades should be ordered as the MC88916DW70 and MC88916DW80, respectively.
From what I can tell from my researching the chip (used on my Interware Booster30-33Fv2, though mine is a 70) is that it offers several output clock signals based on the input SYNC signal. Most of the output lines are clock doubled, but there's one "2Q_X" that is clock quadrupled from the input SYNC signal. So, the 55, 70, 80 part rating is indicating the max frequency of that quadrupled signal that the chip is binned to handle.
Gotcha. So it sounds like the -55 value might could be a limiting factor on these Centris boards. I'm fairly certain an 800 will have a -70 part as well, but MrKSoft is going to check on theirs. Out of curiosity I just checked what's on the 840av board, and it's got an -80 partAdditional fancy things can happen on the buffer like dividing or multiplying the original clock for all or just some of the output clocks. Depends on the buffer chip and the system requirements. It sounds like some components on Wombat are using the straight system clock, but at least the CPU (?) needs a clock signal at twice the bus speed. Hence that 2Q_X signal.
I think I could. I've done some other 20 and 24 pin versions on a HD controller board, but I'll need to do some extra insulation on the nubus slot. Mine's not 'bad', but there's definitely some micro deformation on the end. This will be smack in the middle.Do you feel comfortable replacing that chip? It would be interesting to do thorough speed testing on both machines and then replace the MC88916DWs with the -80 version and see if it makes any difference in the performance.
I only have a 22.1184 crystal, and that may just be enough to cause problems.
I haven't the slightest clue, but my best guess would be that it's an exploration of potential overclock configurations that aren't possible with normal techniques, which don't account for the potentially beneficial changes in djMEMC timings which are activated by the unused gestalt IDs.Purely for my own edification: what exactly are you guys doing with these souped-up 44 MHz Quadras that you aren't doing at 25 MHz?
What are we doing with our vintage Macs that we can't do with FPGAs or software emulation?Purely for my own edification: what exactly are you guys doing with these souped-up 44 MHz Quadras that you aren't doing at 25 MHz?