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Wombat (650, 800) board overclocking limitations


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Possibly. I mean bbraun was able to patch it so you could cram in 128 MiB sticks, giving a 68k Mac half a gig of RAM! o_O

I can't find it now, but in looking up all of these search results for something, I noticed it mentions that the djMEMC will actually change wait states to accommodate slower RAM... So I wonder if there's a (slim) chance of hacking it—adding another machine to the table?— something that could enable it to handle a full 50MHz and still keep itself together... Maybe even handle a proper L2 cache...

Not that I have the programming acumen to even make this happen. also not opposed to doing with or learning how to program, but boy what a deep end dive for a first timer :S

I wonder if that's what those unused Gestalt IDs are; those "speedbump" registers.


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Aha! I found the non-Performa Quadra PDS connector: KEL 8807-140-170xx series | a 140-pin dual-edge connector | the 8807-140-170LH is, I believe, the card-side connector.

KEL connector series catalog: https://www.kel.jp/files/user/product_design/assets/pdf/380_ext_19_en_0.pdf

Annnnnd it's more expensive than I originally recalled it to be (prices from DERF Electronics in the US):

1 - 10$32.50
11 - 50$29.25
51 - 100$26.325
101 - 500$23.693
501 - 1000$21.323
1001 - 2500$19.191
2501 - 5000$17.272


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There's also a bbraun memory fix to use 128 MB modules (!) relative to the DJMEMC, but I don't know if that's strictly speaking relevant here.

Well thanks for that. 😉 I've been trying to remember mac68k.info. There's also another similar site. Want to say it had 'classic' in the name, but not sure. Just lost 30 minutes reading old threads. Had to use will to pull myself out.

BTW, I think Rob has a type in that wiki article. He says, "The Mac ROM will only ever initialize the djMEMC with bank configuration registers bit 8 set to 1." I think he meant "set to 0.". Or he meant, "will never initialize".


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I made it up into the attic. The 1M X 4 memory chips are 60ns. Oki brand, M514400D-60SJ. You might want to check whether that's the needed configuration (1M X 4). 8 chips provides 1M X 32 => 4MB of memory in 1 bank.

I'm not sure I'd start soldering them to a motherboard without a RAM tester. They're probably all good, but one bad chip could be a diagnostic nightmare.

Or, if you do try the swap, swap one chip at a time and test the motherboard after each chip swap.

I guess these can probably be used to fill out boards that only have 4MB as well.

I'll try to post a datasheet later.


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Aha! I found the non-Performa Quadra PDS connector: KEL 8807-140-170xx series | a 140-pin dual-edge connector | the 8807-140-170LH is, I believe, the card-side connector.

The 8807 has male plastic (interior fit). The 8817 has female plastic (exterior fit). Does the card side fit over the motherboard connector, or into the motherboard connector?

Nice find, by the way. But, yes, pricey. Not terrible if you just need a couple of them, but if you had a project where you wanted to run off 100, $2600 just for the connectors is a lot of money up front.


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The 8807 has male plastic (interior fit). The 8817 has female plastic (exterior fit). Does the card side fit over the motherboard connector, or into the motherboard connector?
I stumbled on it in the 610/650/800 Dev Note PDF, here's a direct quote [page 36 (48 of the PDF)]
The 68040 PDS connector is a 140-pin connector manufactured by KEL Connectors, Incorporated. The connector on the main circuit board is KEL part number 8817-140-170SH; the corresponding connector on the PDS card is part number 8807-140-170LH.
So it looks like the 8807 is the 'male' connector for the PDS card. It's a weird design though lol. It does sit 'in' the logic board 8817's connector, but card connector still 'receives' the connectors from the board. Okay, KEL, lol.

I think at some point there was talk of reproducing, but it was probably nuked. I know at least two (active) members have either the DayStar or whichever other brand was making them (briefly). From what I can find, Sonnet's QuadDoubler was a much better value: faster 040 (plus cache on some versions). Those contemporary "unfavorable" reviews really strike me as odd, since the Carrera + cache is screaming... I'm probably repeating myself already.

Pages 37-38 (49-50 of the PDF) also have pin assignments, "nonmicroprocessor signals' table, 'restricted microprocessor signals', and even specifications (dimensions) for the WLCD (610) right-angle adapter and usable space for card I/O. Linked above. Some tidbits for the more able-minded and industrious...

You might want to check whether that's the needed configuration (1M X 4).

Looks like that's the ticket: 1M x 4

Can't say I have a RAM tester. Don't suppose you have one and I can pay you to test them?


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@jessenator It's nice when the Hardware Developer Note spells it out for us.

I don't have a memory tester. I was going to get a SIMMCheck or RAMCheck tester, but I talked to my friend/coworker who used to do memory testing and he recommended I look for a DarkHorse tester. It looks like the Sigma-LC would be the one. Found one on Ebay immediately at a good price, but after I bought the seller came back and said upon examination it was in more or less demolished condition. Looks like it got crushed by something hard at some point.

I haven't seen one since. Sigh.

Anyway, these chips are still on the reel, so they ought to be good. The only concerns would be normal failure rate for new parts (should be extremely low) and whether sitting unused for 20 years would cause any failures.


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This is turning into a multiplicity of things Quadra : P and I'm continuing to contribute to it.

It looks like some of this was saved, as it was 2020, but I don't think we went into details—

So here's what I have so far as the DayStar QuadraCache

I was looking up the memory: IDT 71B256 SA 15[0ns] Y ( 32k x 8 ) SRAM (a suitable replacement?)
@Bolle seems to have cracked the one GAL, documented here, since it may have been lost on here?
the PALs (here's my ignorance showing) I'm guessing need to be programmed… here's the P/N from ti.
U9 is a "BCD-to-decimal decoder"? I'm not sure. I had a real link tag game going to get to that endpoint… ti makes them, but not in a 20-SOP package… I'm really out of it now. Are any of these what might be needed?
U10 and U11 (L7C174WC15) is "x8 Cache-Tag RAM" found on UTSource.
U12 and U13 is a buffer? Corresponding to this newer equivalent.


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I think U9 is an octal D flip flop. Try 74F574.

I have about 450 32K X 8 SRAM on hand. Alas, they are 20ns, not 15ns. Sigh.


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On the TNT motherboards, the Gestalt changed depending on where you put the power LED. In the front and it’s a 7x00, on the side and it’s an 8x00. Some motherboards, the Gestalt changed depending on just the processor speed or type. It’s voodoo as far as I can tell.


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It’s voodoo as far as I can tell.
It's hard to believe that folks worked this stuff out the way they did in the day with risk to working machines! I'm sure any of that info hasn't been leaked from internal docs, and certainly not in their day. I doubt Apple wanted users to know that the difference between a Centris 650 and a Quadra 800 was (simplistically, I grant you) two cheap components.

Internal, NDA-protected documentation would assuredly have it for production/manufacture. *sigh* one can dream of leaks, right?

In the front and it’s a 7x00, on the side and it’s an 8x00.
Probably a similar type of switch to the Wombat: the LED for the 800 surely doesn't need 5 pins, but two of them are a jumper, as posted earlier.

But all the same, modifications known and unknown, they were never as simple as the PCs of the era: a few jumpered pin headers and you're off to tweakland™. But then, that's a whole other design philosophy ballpark.

And for sure Apple had a very ...insular approach to board making. I want to say that the LPX-40 (Tanzania) was about as close as they ever came to an 'industry standard,' as it's a derivative to the short-lived LPX from factor. At least the dimensions and mounting, clearance, etc. are the same. But that was a co-design with Motorola who wanted CHRP/PReP business... and then Jobs came back : P

Some Apple boards were meant to be versatile (e.g. Wombat, WLCD), and others strictly their own (Quadra 700, Power Mac 7100). While perhaps not all-inclusive as far as Gestalt ID, this is a good reference for PowerPC board designs: https://macinfo.de/hardware/hardware.html —use Chrome or a translator plugin as the page is auf Deutsch.


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OKAY I think I actually have a good idea what's going on! I mean, not perfectly, but I think I have a better understanding of how things are working here!

In an effort to just comprehend what is happening on the boards, I kept going back to that Universal ROM module document and trying to find connections there. At one point I was going to hypothesize which aspects of the ROM need to be changed to add an additional Machine ID, but I'm not sure if we need to… we'll see!

I was looking at the DRAM timing table and noticing how it takes the clock into account when adjusting the timings, and then I thought, well, the actual percentage increase of the timings for the overclock of @Mr. Ksoft 's 800 33 running at 44 MHz are higher than @cy384 's 650 (w/ 40MHz CPU) running at 44, and wondered why there isn't more headroom. AND THEN IT DAWNED ON ME.

The @MachineTbl has two "unreleased" models—their 'speedbump' versions of the Q800 and the Q650. The clock chipping guide has two unknown/unused Gestalt IDs! THAT'S WHAT THE UNUSED GESTALT IDs ARE FOR! These 'SpeedBump' models! Each of them!

These models are meant to be run at 40Mhz at the ROM level! That means all of the timings would be adjusted to operate at a higher faster clock, faster DRAM, etc.!

I know why your overclock @cy384 wasn't working above 44 Mhz! The ROM is telling the djMEMC that you mac is still technically needing to operate at 33 Mhz! Regardless of what the actual clock is outputting to the CPU to run at, the rest of that low-level operational instruction is telling it to behave like a Quadra 650! It's trying to overclock the DRAM to a point where it won't be stable!

I've got to take off, but I wanted this word vomit to get saved! Check out what I'm talking about in this Google Sheet.
I'm going to make this part of my testing! I know the Gestalts weren't supported for system 7 without Marc's patch to the 040 enabler, but it might just work with 8 unpatched!


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The @MachineTbl has two "unreleased" models—their 'speedbump' versions of the Q800 and the Q650. The clock chipping guide has two unknown/unused Gestalt IDs! THAT'S WHAT THE UNUSED GESTALT IDs ARE FOR! These 'SpeedBump' models! Each of them!
OKAY elaboration time.

So, inside of this module relative to the Macintosh Universal ROM (starting at line 809), there are a number of tables identifying aspects of the computer which (how I understand it) are communicated to the djMEMC on Wombat boards (I'm going to skip over the items relevant to the WLCD and Cyclone / Tempest boards) and determine a number of important component timing figures. Several tables that are associated with several properties (I'm sorry if you're a programmer and I'm butchering nomenclature here):

@dj20Config    dc.w    %0000000100000001    ; fastwr=1, ROMspeed=1
@dj25Config    dc.w    %0000000000011010    ; drpchg=1, drpw=1, ROMspeed=2
@dj33Config    dc.w    %0000000010100011    ; mhz33=1, cyc23ta=1, ROMspeed=3
@dj40Config    dc.w    %0000001011110100    ; dwcpw=1, mhz33=1, drcpw=1, cyc2ta=1, drpchg=1, ROMspeed=4

@dj20Refresh    dc.w    285    ; (20MHz * 15.6µs) - 27
@dj25Refresh    dc.w    363    ; (25MHz * 15.6µs) - 27
@dj33Refresh    dc.w    487    ; (33MHz * 15.6µs) - 27
@dj40Refresh    dc.w    597    ; (40MHz * 15.6µs) - 27

@MachineTbl                        ; Type   CPU VIA ID
    dc.b    @DJ_ORIG,%00010010    ; 33MHz Frigidaire package (Quadra 800)   
    dc.b    @DJ_BUMP,%00010110    ; 40MHz Frigidaire package (unreleased)   
[redacted for clarity]
    dc.b    @DJ_ORIG,%01000110    ; 25MHz Lego package (Centris 650)
    dc.b    @DJ_BUMP,%01010010    ; 33MHz Lego package (Quadra 650)
    dc.b    @DJ_BUMP,%01010110    ; 40MHz Lego package (Quadra 650 SpeedBump, unreleased)    <SM60>
    dc.b    @DJ_ORIG,0            ; if here, this is EndOfTable
                                ; VIA CPUID of 0 is a reserved (unused) machine.

@bump20Config    dc.w    %0000000100000001    ; fastwr=1,                                              ROMspeed=1
@bump25Config    dc.w    %0000000000011010    ;                                      drpchg=1, drpw=1, ROMspeed=2
@bump33Config    dc.w    %0000000011111011    ;          mhz33=1, drcpw=1, cyc2ta=1, drpchg=1  drpw=1, ROMspeed=4
@bump40Config    dc.w    %0000001011111100    ; dwcpw=1, mhz33=1, drcpw=1, cyc2ta=1, drpchg=1, drpw=1, ROMspeed=5

So we have a swath of properties that cover the gamut of the Centris/Quadra lineup: planned clock speeds (from the lowly Centris 610 all the way up to the 'Cyclone' 840av), DRAM timings, ROM(?) speed(timing?), and a few other properties I haven't seen elaborated upon. Pay attention to the number of machines in the @MachineTbl.

The Wombat boards came in two flavors, if you will: "Figidaire" (also referred to as "inTheFridge" or "fridge") and then "Lego" based on whichever case they were to end up in. They came in three (shipped) configurations at two clock speeds: 25Mhz and 33MHz. There are also two 'unreleased' configurations, both at a 40Mhz clock. These are not the 840av/Cyclone, these are Wombat configurations.

My first hypothesis is that these make up the five Gestalt IDs from the archived clock chipping guide. The ones that don't work with System 7.5 without an enabler patch are these 'speedbump' 'bump' machines:

In cases where someone chips the CPU to operate at a higher-than-stock speed, they have two changes to make. If it's a "@DJ_ORIG,%01000110" machine (i.e. Centris 650), they cannot go beyond 30 Mhz, and must switch the board's Gestalt to either a Quadra 650 or 800. If it's already a Quadra, there's no need for that change, however, the second change is altering the on-board clock oscillator. As far as an 'overclock' is concerned, that's the job done. We have ample accounts of folks chipping their quadras to the supposed limit of 44 Mhz, even with a comparatively faster CPU installed.

Here's where a second hypothesis comes into play.

When you have or change to the Gestalt IDs 35 or 36, the ROM is communicating to the djMEMC (memory controller) to expect a machine running with a CPU clock of 33(.333)MHz, and will adjust the relative board component timings accordingly to that set of figures from ROM, not to the relative clock you have set via the oscillator. Therefore, you're not overclocking it from the timings of a 40Mhz machine, you're overclocking it from the timings from a 33MHz machine!

So here we see that attempting to reach 50 MHz in this situation, you're putting tremendous strain on the timings and opening up a chasm for errata and system crashes. This is the reason, I hold, that these overclocks haven't been possible for Wombat Macs.

That last column, in particular, is the key point: If hypothesis 1 is correct, choosing a Gestalt ID of 51 or 59 will essentially tell the djMEMC to set the timings for an actual 40MHz Mac and chipping said Mac to 50Mhz will theoretically only push a DRAM timing overclock of 126%—well within the boundaries of what has been proven by solutions like OutputEnablers or MacClipJr on other Centris and Quadra Macs:


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Interesting stuff and tracks a little bit with the fact that the PowerMac X500/X600 machines have 3 "CLK_ID" pins on the CPU card. These pins are Grounded (or not) on the CPU card and signal the Hammerhead memory controller in what speed realm to operate, by increments of 5MHz.

On the PowerSurge family (X500/X600 machines) the Clock is on the CPU card. Change the CPU card and the clock could be anything. So they couldn't set the timings according to the computer model.

So there had to be some way for the CPU card to tell Hammerhead what the Clock is. Hence, the Clock ID pins.

In the early days, the upgrade makers didn't know about Clock ID pins. And so even though many G3 upgrade cards could have their clock adjusted by the user (switches, jumpers on the cards) the users were finding that they really couldn't go much past 45MHz bus speed.

The upgrades were adjusting their clocks, but not telling Hammerhead about it.

XLR8 knew about it with their PPC604E upgrade. Their PowerBoost Pro contains a PIC on board. As you adjust the clock speed up, it changes the CLK ID pins. I can run a PM9500 or Umax S900 with a 62+MHz bus speed, using a PowerBoost Pro. (May be misremembering the name of the upgrade).


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Ok, you got me hooked, I just wrote a little program that reads the values out of the djmemc configuration registers. Here's "ultra-wombat-hax-tool" which you can also download, for the moment, from http://www.cy384.com/media/bin/ultra-wombat-hax-tool.bin (I'll put the code and whatever on github tomorrow or whenever). And here's the data from my machine (the 44mhz, resistor-converted from C650 to Q650, with 4x32MB plus 8MB on-board):


No promises the code is correct, didn't consider stuff like byte order, it's all offsets from the djmemc base addresss, read as 32 bit ints and printed as binary.
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I think the question is now: does a gestalt of 59 (or maybe 51) convince it to load the speedbump values?
Only one way to find out, I suppose

My assumption in that ID 59 corresponds to the Frigidaire / Quadra 800 speedbump is that its ID set with the LED jumper, which would already be in place for the power LED on a minitower case. ID 51 would perhaps then be the safer one to start with, as I haven't yet soldered on the 60ns RAM @trag so graciously sent me: The comment starting on line 23 implies that any non-Fridge Wombat can take 80ns RAM, while an IDed Fridge Wombat requires 60ns.

One thing I hadn't thought of: what happens if the CPU clock (read: oscillator) is lower than what is expected? I suppose it would just freeze during boot or even just fail the memory test... I can easily solder in my just-arrived 20.0000MHz XTAL and pop in the RC40 CPU.

I was planning to also do some RAM testing as part of this... I wonder then, would pushing the DRAM refresh that far past the designed-maximum of 597, beyond the currently-stable-overclocked-maximum of 660, all the way to the theoretical maximum of 753 benefit from faster DRAM?

I mean, we know that 650s and 800s both can do 660 (what the heck is that number to be measured in anyway, Hz? KHz?), but now we're moving beyond. I mean, an 840av can go to 48Mhz clock / 722 refresh it seems...

How about this:
  • Test 1: convert Wombat board to Gestalt ID 51; Replace clock osc with 20 MHz sample; Use MC68040RC40 (E42K) CPU; run "ultra-wombat-hax-tool" and collect results of MEMCconfig; (that's assuming it will boot, though it should...)
  • Test 2: replace clock osc with 25MHz specimen; test POST; if YES test boot and stability; if NO replace clock OSC with 24MHz specimen and incrementally down till system stability is YES
  • Test 3a: replace on-board RAM with 60ns specimens; replace clock OSC incrementally up until system stability is NO or 50MHz clock and system stable is YES
  • Test 3b: replace on-board RAM with 60ns specimens; convert Wombat board to Gestalt ID 59; replace clock OSC incrementally up until system stability is NO or 50MHz clock and system stable is YES