• Hello, Guest! Welcome back, and be sure to check out this post for more info about the recent service interruption and migration.

Wombat (650, 800) board overclocking limitations

cheesestraws

Well-known member
it's like with each successive Quadra/Centris iteration, they kept consolidating chips into new ICs

This is a general trend across computing at the time: Apple were doing it aggressively but they were far from the only ones.

the SCC IC is present in the Wombat, as well as Quadra 700, IIci, and I'm not sure how far back

The SCC family of ICs are used all the way back to the original Macintosh (and on the Lisa, too). When things got integrated onto fewer, larger ICs, it was still pretty much an SCC on that IC, it was just sharing silicon room with other cores. Geoport makes things more complicated, but you still have what boils down to being an SCC in there somewhere in the mess :).
 

jessenator

Well-known member
xoITk4Q.jpg
 

jessenator

Well-known member
It interprets the bits and nicely prints a little more info.
Nice work!

so is all of this "digestible" text direct output from the djMEMC? even the parenthetical comments? e.g. "(ideal for 32 ish MHz)"
syqAtSz.gif


I set mine to be a Quadra 650 for the time being. I need to suss out which components can tolerate the overclocks, because with my initial trial with all of the oscillators I have didn't go as expected. I don't know if it's RAM, SCC, or otherwise. So I'd like to eliminate/check variables in a less haphazard manner, compared to what I've been doing, in my zeal : P Testing things on each Gestalt ID as suggested by @cheesestraws over IRC the other day, might be a more sensible approach. Although I wonder what willl happen at 35 or 59, when it 'expects' a different RAM speed… I guess we'll find out.
Z4ZocbMt.gif


I do like that TechTool (1.2) does identify the Gestalts correctly. So here's my 'Quadra 650' per MacTest Pro (36):
CSILKBE.gif

or improvises on my 'unknown type' per MacTest Pro (51) :D :
i7jPNBV.jpg
 

cy384

Active member
so is all of this "digestible" text direct output from the djMEMC? even the parenthetical comments? e.g. "(ideal for 32 ish MHz)"
all of the stuff it prints is read from the registers or reported by the OS, the "ideal for XX mhz" takes the number of cycles in the register and basically reverses the calculation described in the ROM comments (+/- rounding errors)

there are like 6 different ways that the ROM seems to set the config register, so it prints the name from the ROM source if it matches one (e.g. "dj33Config")

obviously some things will remain mysterious, like the meaning of the config register bit names, but it's nicer than just seeing the 1's and 0's
 

jessenator

Well-known member
Check what version of the MC88916DW is installed.

This is the one on the OE Centris 650 board where I'm testing:
CqEIyjLm.jpg


This is the one on the OE Quadra 650 board I have:
I4XccqBm.jpg


Maybe I was too quick to write off @cy384 's suggestion that the on-board components have different specs… -_- my apologies.

"ideal for XX mhz" takes the number of cycles in the register and basically reverses the calculation described in the ROM comments (+/- rounding errors)
Gotcha. Well that will definitely be something to check against during the refined testing process.
 
Last edited:

jessenator

Well-known member
This is the one on the OE Centris 650 board where I'm testing:

Well this is interesting… (from the datasheet, emphasis added)
The MC88916 Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for CISC microprocessor or single processor RISC systems. The RST_IN/RST_OUT(LOCK) pins provide a processor reset function designed specifically for the MC68/EC/LC030/040 microprocessor family. The 88916 comes in two speed grades: 70 and 80MHz. These frequencies correspond to the 2X_Q maximum output frequency. The two grades should be ordered as the MC88916DW70 and MC88916DW80, respectively.
I have a hunch of what this means, but can you shed some light, @trag ?

It's also interesting that "55" (from my p/n) doesn't appear on this sheet…
 
Last edited:

Nathan_A

Well-known member
Well this is interesting… (from the datasheet, emphasis added)

I have a hunch of what this means, but can you shed some light, @trag ?

It's also interesting that "55" (from my p/n) doesn't appear on this sheet…
From what I can tell from my researching the chip (used on my Interware Booster30-33Fv2, though mine is a 70) is that it offers several output clock signals based on the input SYNC signal. Most of the output lines are clock doubled, but there's one "2Q_X" that is clock quadrupled from the input SYNC signal. So, the 55, 70, 80 part rating is indicating the max frequency of that quadrupled signal that the chip is binned to handle.

So, if yours is rated at 55 Mhz, then that means if you intend to use the "2Q_X" output clock, then your max input SYNC signal is 13.75 Mhz.
 
Last edited:

trag

Well-known member
@jessenator Clock buffer chips are pretty common on computer systems.

Imagine a bus with several different devices on it, which operates synchronously. I. e., they're all expected address/data phases at a particular time in a particular relationship. How do you give all those separate chips a concept of time like that?

Obviously, you hook them all up to the same clock. But there are details. It turns out that the drive strength from a single oscillator isn't all that strong. And some chips need the signal doubled or halved for various logicy reasons.

So, clock buffer chips.

A single clock signal goes in. In theory everyone is running off that one signal. The buffer chip takes that one signal, and splits it into several identical signals which are all in phase with each other, to some very small tolerance and each of the chips on the bus gets its own clock from that buffer chip.

Additional fancy things can happen on the buffer like dividing or multiplying the original clock for all or just some of the output clocks. Depends on the buffer chip and the system requirements. It sounds like some components on Wombat are using the straight system clock, but at least the CPU (?) needs a clock signal at twice the bus speed. Hence that 2Q_X signal.

I haven't looked closely at the datasheet for the MC88916DW, and how WomBatman does things, but, for example, on the X500 Power Macintoshes, which have their CPU on a removable card, the clock signal also originates on that card. That way, the CPU card one installs controls the bus speed.

But in practice, the way that is done is that six (6) different clock pins exit the CPU card and go out to components on the motherboard. Every CPU card for the X500 series has a clock buffer chip on board that splits the clock signal at least 7 ways (one extra for the CPU on the card).

On the PPC601 chip, the chip does not have the ability to multiply its input clock, the way later PPC chips do, so if you have a bus speed of 33MHz, and you want the PPC601 to operate at 100MHz, then you need a clock buffer that can supply an X3 clock signal to the PPC601 chip.

Anyway, I didn't realize that the datasheet for the MC88916DW doesn't cover the -55 version. I know it exists because I have a reel of five or 6 hundred of them here. I've been wondering what I can do with them, since they're the slow version. Not going to replace the fast version with the slow version.

Do you feel comfortable replacing that chip? It would be interesting to do thorough speed testing on both machines and then replace the MC88916DWs with the -80 version and see if it makes any difference in the performance.

I think I have some of the -80 on hand. I need to check, but if I do I could send you a couple.
 

Nathan_A

Well-known member
Here's the diagram from the datasheet that helped me make sense out of what's going on with the MC88916DW:


Screenshot_20210813_130331.png
 

jessenator

Well-known member
Additional fancy things can happen on the buffer like dividing or multiplying the original clock for all or just some of the output clocks. Depends on the buffer chip and the system requirements. It sounds like some components on Wombat are using the straight system clock, but at least the CPU (?) needs a clock signal at twice the bus speed. Hence that 2Q_X signal.
Gotcha. So it sounds like the -55 value might could be a limiting factor on these Centris boards. I'm fairly certain an 800 will have a -70 part as well, but MrKSoft is going to check on theirs. Out of curiosity I just checked what's on the 840av board, and it's got an -80 part
1628887578054.png Thanks, Bruce for the high res image of the mobo I snapped this from!

Do you feel comfortable replacing that chip? It would be interesting to do thorough speed testing on both machines and then replace the MC88916DWs with the -80 version and see if it makes any difference in the performance.
I think I could. I've done some other 20 and 24 pin versions on a HD controller board, but I'll need to do some extra insulation on the nubus slot. Mine's not 'bad', but there's definitely some micro deformation on the end. This will be smack in the middle.

With the MacClip on its way, adjusting clock input won't be as tedious. So yeah, I think it could be a hopeful avenue to test down. I've thought of first getting out the (native) Quadra 650 board and making it WomBatman, and then running the tests on it.

The -70 part should be good up to 46.66 MHz — I have a shaky theory that 44 MHz is the narrow margin for the -55 p/n PLLs (which by math should have a 36.6666 MHz peak). As others who have converted their Centris boards to Quadras can stay level 44 Mhz with a 22.0000 input clock, there's some things I want to test first. I only have a 22.1184 crystal, and that may just be enough to cause problems.

Here were my manual-resoldering-the-oscillator test results so far:
qAFIh8xh.png
 

LaPorta

Well-known member
Purely for my own edification: what exactly are you guys doing with these souped-up 44 MHz Quadras that you aren't doing at 25 MHz?
 

CC_333

Well-known member
It looks like your board really doesn't like the OC refresh Frequency to be any higher than 597! Is it due to this:
I only have a 22.1184 crystal, and that may just be enough to cause problems.

Purely for my own edification: what exactly are you guys doing with these souped-up 44 MHz Quadras that you aren't doing at 25 MHz?
I haven't the slightest clue, but my best guess would be that it's an exploration of potential overclock configurations that aren't possible with normal techniques, which don't account for the potentially beneficial changes in djMEMC timings which are activated by the unused gestalt IDs.

c
 
Last edited:

jessenator

Well-known member
Purely for my own edification: what exactly are you guys doing with these souped-up 44 MHz Quadras that you aren't doing at 25 MHz?
What are we doing with our vintage Macs that we can't do with FPGAs or software emulation? 🙃

For me, I'm doing it to see if there's an avenue of overclock that hasn't been tried, or some aspect that wasn't tested/known about. Maybe, maybe not. Pushing limits within reason.

In parallel I'm hoping to learn more. Computing, programming, hardware design—this is how I do: immersion, deep diving. I know it's mildly insane, but here we are. 🤣

Paramount is my desire to do no harm to the board, of course.
 

Mr. Ksoft

Well-known member
Well guys, I have my results, and I'm going to confuse everyone possibly. My Quadra 800 has... the XC88916DW55. And yet, not only has it run happily at 44mhz... jessenator encouraged me to try some of the undocumented DIP switch settings on the MacClip and now the machine is running at 45mhz! (This seems to be the highest setting allowed using the MacClip). I didn't expect to see the -55 PLL in there... I feel like this throws a wrench in some theories, or I'm just lucky for now and this thing's going to blow up after a few hours :)

List all possible frequencies:
Dip switches listed 0 for off, 1 for on, left to right: 1-2-3-4
  • 0000: 25mhz
  • 0001: 38mhz
  • 0010: 29mhz
  • 0011: 42mhz
  • 0100: 26mhz
  • 0101: 40mhz
  • 0110: 31mhz
  • 0111: 44mhz
  • 1000: 26mhz
  • 1001: 39mhz
  • 1010: 30mhz
  • 1011: 43mhz
  • 1100: 28mhz
  • 1101: 41mhz
  • 1110: 32mhz
  • 1111: 45mhz
Should also note that the manual for the MacClip lists 40mhz as "0111" which is how I ended up at 44mhz in the first place. The other options printed for the Q650/Q800 (38, 39, 41mhz) are all accurate.

I have not had time to test the system extensively at 45mhz, but networking, sound, video (both internal and NuBus) and serial MIDI all worked fine.

Screenshot for proof:

45mhz!!.png
Also here's the ultra-wombat-hax-tool output:
UltraWombat-Q800-45.png
 
Top