bear
Well-known member
10 address lines are needed for 4 Mbit x 4 DRAMs, so I'd say you're good to go. (If you're making 16 MB on a 32-bit data bus out of 8 chips, you have 4Mx4 parts. TMK nobody made a 2 Mbit x 4 DRAM chip, since it still requires 10 address lines, but in a degenerate arrangement).
As long as the support logic in the chip can identify the size correctly (and consequently is able to direct the CAS signals to the correct bank based on the physical address) and the 10 address lines are indeed brought to the pads for the Bank A memory, it ought to work. You said this is the same support chip used in a less compromised system, so it'd be surprising if it didn't work.
As long as the support logic in the chip can identify the size correctly (and consequently is able to direct the CAS signals to the correct bank based on the physical address) and the 10 address lines are indeed brought to the pads for the Bank A memory, it ought to work. You said this is the same support chip used in a less compromised system, so it'd be surprising if it didn't work.