Memory Addressing Questions

[bear]

10 address lines are needed for 4 Mbit x 4 DRAMs, so I'd say you're good to go. (If you're making 16 MB on a 32-bit data bus out of 8 chips, you have 4Mx4 parts. TMK nobody made a 2 Mbit x 4 DRAM chip, since it still requires 10 address lines, but in a degenerate arrangement).

As long as the support logic in the chip can identify the size correctly (and consequently is able to direct the CAS signals to the correct bank based on the physical address) and the 10 address lines are indeed brought to the pads for the Bank A memory, it ought to work. You said this is the same support chip used in a less compromised system, so it'd be surprising if it didn't work.

 

[bear]

Ah. I just realized you're referring to the DRAMs as 2 megabyte chips, which I suppose is technically correct, as their total capacity when measured in 8-bit bytes is 2048 KB. But this is a misleading designation, because there are other--incompatible--ways to get a 2 megabyte DRAM, such as 1 Mbit x 16.

 

[uniserver]

Part number HYB514100BJ-60

Category

Description 4M X 1bit DRAM

Company Infineon Technologies Corporation

Datasheet Download HYB514100BJ-60 datasheet

Request For Quote Find where to buy HYB514100BJ-60

 

[Trash80toHP_Mini]

Uni, did you try the IIsi using the Vampire Video for the test? If, so slap a Pivot card in there, unhook the cable from the onboard connector and test again.

Done that way, you ought to have a much better chance of it working.

edit: I finally put the probes onto the memory pins of both banks and MDU.

MoBo powered down:

_____74ALS245 buffers at rest

__________Bank_B_pin_4_A0 -> MDU_pin_70

__________Bank_A_pin_6_A0 -> MDU_pin_69

So Bank A Addressing is indeed separate from Bank B Addressing with the buffering ICs in this state.

Can I safely add power from an outside source to the 74ALS245 bus buffer ICs to test the other two states? Individually or separately? Alternately, I could remove de-solder/isolate/power up the VCC leg of the appropriate 74ALS245 a/o DRAM IC? Most radical approach would be to desolder the and 7fALS245 and build a test circuit board with an old school 74LS245?

edit: Does anyone have a link to such a DIY bus testing circuit board, such would be a tremendous help in ferreting out the address and control lines for the 2300c and 1400 for the Video and PCMCIA hacks. [] ]'>

 

[bear]

Er, no, 8 4Mx1 chips isn't going to work for bank A in a IIsi. You have installed an 8-bit wide memory; 24 data lines are not connected to anything, even assuming the rest of the pinout is the same (which I doubt).

I've been posting too late at night and some of the other things I wrote about required address bits and memory sizes are not correct, because I was not keeping sets of facts straight. I'd start writing one thing and finish writing another. I should probably unwind it and write a correction.

 

[Trash80toHP_Mini]

That would be great, thanks for your help, bear. I've been doing the same late night thing, but early AM as well . . .

. . . burnin' away at both ends of the candle. :-/

We've also got discussions about these DRAM ICs going in two other threads, one about the IIsi, like my questions in this thread and and about the Q605/LC475 in the other. Makes for a nice mess!

 

[Trash80toHP_Mini]

OK, I've got a request for help with buzzing a csome connections an one of the two machines I don't have that use the MDU Memory Controller ASIC:

on the IIci & SE/30 there will be a square, 128pin, Quad Flat Pack IC between the CPU and Memory Banks A&B, that's MDU

Pin 17 of MDU is connected to pin 19 on the SIMMs in Bank B - RA10

Pin 16 of MDU is connected to pin 19 on the SIMMs in Bank A - A10 - Yes or NO?

Pin 13 of MDU is connected to pin 24 on the SIMMs in Bank B - RA11

Pin 12 of MDU is connected to pin 24 on the SIMMs in Bank A - A11 - Yes or NO?

WAG:

Please check to see if pins 4,5,8 and 9 of MDU are connected to anything in either SIMM Bank and if so what pins?

Anybody got a hopelessly DOA IIci or SE/30 board to trade for some trinket in my hoard? [)] ]'>

 

[bear]

Trag basically wrote the correction post I was writing, and beat me to posting it. It's in the Q605 thread.

 

[Trash80toHP_Mini]

Yep, but I'm not trying to beef up Bank A on the MoBo at that location.

I'm making adapters to install four double banked 72-pin SIMMs in the slots of Bank B. The first bank of the 32MB, 72 pin SIMM will act as a 16MB 30-pin SIMM in bank B as "usual." The second Bank of each will act as a 16MB 30-pin SIMM in Bank A as in an SE/30.

Since the CPU/MDU can only address Bank B or Bank A on any given cycle, I need to figure out how to multiplex the address and control lines on the adapter using an existing or synthesized Bank Select signal on each of the four adapter. I'm working out how to get around the Vampire Video's Data Line buffering next.

Next to worst case will be implementation of a fifth circuit board multiplexing all the Bank A signals and reflecting them back at the SIMM slots of Bank B.

Worst case would be not being able to get Bank A to work on the adapters in the IIsi, winding up with a way to make inexpensive 16MB SIMMs for Bank B and to max out my Quadra 950 without going broke in the process.

Dunno, but the ersatz Memory line layout/fleshed out Memory schematic I'm building in Illustrator for the project is a pretty neat exercise for learning a bit about Memory Subsystems! )

 

[Trash80toHP_Mini]

30pinMESS.2p.jpg[/attachment]

. . . much work to be done on the blocking diagram of the Bank A end of things before I can make any real progress on the adapter end. :

 

[Trash80toHP_Mini]

Holy crap!!!!! 8-o

[attachment=0]SSIMM_pinout_comparison.2p.jpg[/attachment]

No wonder the industry switched over to 72-pin SIMMs ASAP! :

 

[Trash80toHP_Mini]

I guess if you keep banging your idiotic head on the 22" CRT you can finally get somewhere . . .

of[/i] the SE/30 :-/ >

 

[Trash80toHP_Mini]

'>

 

[Trash80toHP_Mini]

More questions:

Since both Bank A and Bank B run their data lines through the 245s, I'm WAGgin' that I'll need to create a similar circuit inside the illustrated box to Buffer the Address and Control lines and a Bank select signal just like the Data lines are currently gated?

Such a circuit will need to multiplex the address and control lines on the MoBo between Bank B (and my ersatz Bank A converters) to reflect the Bank A lines back over to the disconnected "Bank B" on the 72 pin SIMMs through the existing traces on the MoBo?

I may need to similarly hack the Data Line buffering to work from my relocated "Bank A" as well.

Does any of this make sense to someone? :-/

 

[Trash80toHP_Mini]

Guess not . . . whatever! :lol:

'>

zzzzzzzzzzzzzzzzzzzzzzzzzzzzzz . . . |)

 

[Trash80toHP_Mini]

[attachment=0]Octal_FlipFlop-or-NOR.2p.jpg[/attachment]

Quick question, 74LSXXXX was a long time ago. :/

Do I want to replace the 245s with which choice in the caption or another type to send the Bank A Data Signals back over the Bank B traces?

I'm figuring on using W/E as my bank select and a nasty hack for getting the addressing for bank A to the adapter's Banks at Bank B.

The tiny purple txt and arrows shows where the bank A Data Lines go with the 75ALS245s that need to be replaced to multiplex the Data Lines.

 

[Trash80toHP_Mini]

Hrmmm . . . no suggestions? I really could use some help on the 74ALS245 Buffer IC replacements. :-/

Here's the fugly address line multiplexing hack as it now stands:

MDU Cannot Address Banks A & B simultaneously, nor can it read data from A & B simultaneously (see crude Data Line multiplexing hack above.)

All the address lines for Banks A & B are very conveniently located right next to each other on MDU.

Using Diodes (like backflow valves in plumbing) soldered to the lifted legs of the paired Banks A & B Address signals on MDU, the diodes are then soldered/shorted together and the paired signals are soldered to the disconnected pads of all twelve Address lines heading to the Bank B SIMM Slots. The Banks A & B addressing signals are multiplexed on the Bank B traces by the either/or logic of MDU's limited Address and Data line capabilities.

Add those discrete 24 addressing signals multiplexed over the MoBo's Bank B traces to the 64 discrete Data Lines for Banks A & B multiplexed over the MoBo traces for Bank B and I'm down to a very limited number of Bank A control lines left to hack. I haven't looked at it yet, but I haven't come up with any obvious reason why I shouldn't be able to do the same Diode-Short Multiplexing for the diccrete(?) RAS and CAS lines for banks A & B.

If I can get it down to where I only need to run signals over two patch wires to the two n.c. pins of the 30-pin SIMM spec. I'll be happy!

But if I can get it down to patching just the W/E signal for the Bank A DRAM ICs to just one of those n.c. pins to select the Bank A halves of my adapters for the Double Banked 32MB 72-pin SIMMs while MDU is not enabling same for Bank B for the reasons outlined above, that'd be just about perfect! [}] ]'>

Would somebody PLEASE check out the assumptions I've made above and let me know if this craziness is possible . . .

. . . must I be missing something here? :lol:

 

[Trash80toHP_Mini]

Are the diodes really necessary to buffer the address signals for Banks A & B outputs from MDU.? My original notion was to simply short the two legs together, but I figured having chip driving signals shove back into outputs of an ASIC would probably be a BAD THING.

Is there a convenient little three SMT "nubbin" equivalent of the twisted pairs in the proposed the old school Diode Radio Antenna Farm illustration?

note: I know it's silly (at best) to obsess on getting this project to work, I've already got the Radius Rocket with its onboard compliment of 128MB of interleaved PC SIMMs hacked into the SuperIIsi™ but this proposition is just too delicious to ignore.

If I can get the IIsi to work with the Radius Color Pivot II/IIsi replacing Vampire Video and this hack implemented as planned, I might be able to overclock a IIsi to the point that it outperforms a IIci at its overclocked best. Dunno, but it's yet another fascinating evolution in "tilting at windmills" of the retro-computing world of Apple's hamstrung LEM lineup. [}] ]'>

 

[techknight]

Thats why you should use an OR gate. If either pin goes high, the output goes high.

 

[Trash80toHP_Mini]

Yep, but the way the bank addressing works, they can't both go high at the same time because the Mac and MDU cannot address both banks at once. The OR logic for bank addressing is already built into MDU ASIC to begin with.

Am I incorrect in that observation?

The W/E lines control which DRAM ICs on either 16MB side of the double-banked, double sided 72-pin SIMM will be active and which inactive at that end of the traces.