Ran out the edit clock. :-/
Poking at the ROM might not yield the information. Someone may need to test the theory:
if we build it, they will come . . . online . . . once populated . . . or not.
The LC was ROM limited to 10MB of RAM with malice aforethought. Apple just didn't want a low end Mac running more than 10MB of RAM and needed to cap it that way in firmware to support what we see now as a paltry 10MB allotment because it wasn't possible to do in hardware. There might not be a way to easily limit a 1MB/2MB/4MB capable 16-bit SIMM bus to exclude 8MB SIMM support and from there translating to 16MB SIMM support.
It might not be such a bad way to look at the situation in terms of Apple doing LC/LCII/CC users the favor of supporting 4MB SIMMs at all in a
very low end color Mac. They could easily have flipped them off and capped memory in hardware to 2MB SIMMs with an 8MB ceiling. Such would not have been all that unreasonable a decision in the time frame od the LC release. The cup is 2MB full, not 2MB empty given that perspective.
The IIsi can address 4MB or 8MB in Bank A per the lines available. uniserver did the hack, IIRC 4MB is the physical limit due to unavailability of a DRAM IC to fit the pads on the motherboard to take it to 8MB, likely a pin count thing. That's similar to being able to upgrade a memory starved 128k to 512k because Burrell Smith left the lines on the board for the larger capacity DRAM management had decided to kill for that very first of many RoadApples. It couldn't be taken to 1MB or more for the same reason, no ICs available to begin with and probably memory map problems to boot that early on.
If I'm following you, then yes, the most elegant way of getting four 64MB banks installed on a P/LC 63X machine would be to remove/disable the motherboard RAM, and route the motherboard RAM's RAS line to the SIMM socket which has only a single RAS.
Thanks, I've been wondering about this for quite some time. What makes you say there is only one RAS line per Bank? IIRC there are two for each Bank implemented on MDU.
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One would need to explore whether all four RAS to that socket are tied together. If so, two of them need to be separated electrically and linked to the RAS from the MB RAM.
If F108 is anything like MDU, nothing should be tied together, the problem is more that CAS and RAS lines are parceled out too independently.
I'm not sure about CAS being common. Each bank may have its own CAS as well (may be necessary for refresh control), so the CAS from the MB RAM might need to be rerouted to the single bank SIMM socket as well.
That's where modeling F108 from MDU begins to be problematic. Too tired to take a look at that tonight, There are things like
CAS 1a and
CAS 1b leading to pin 2 on SIMMs 1a and 1b respectively from MDU.
***@trag I'm guessing you can confirm that setup would be required when Bank A is made up of ICs on four individual SIMMs in the 30-pin SIMM architecture and that such distinctions on a 30 line bus would no longer apply to an identical bank of ICs running on a 72-pin bus? Such would seem to be indicated in my mapping of IIsi Bank A. Gotta find that thread and its diagrams. There's also the Quadra 605 72-pin SIMM
EVIL RAS LINE HACK for a more direct comparison.
Then, yeah, just install two 128MB SIMMs and Bob's your uncle.
Might could be. I've always wanted one of these boards to give it a whirl. If I ever relocate my Q630 board with its single SIMM Slot, I may look at patching everything needed from Bank A and F108 to one of my 72-pin SIMM doublers. We're likely talking spaghetti monster for that one I think. [}
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LOL! Forgot to hit "Subnit Reply" last night after fleshing out the bones of the booboo post, must have really needed that ten hours of sleep. :mellow:
