Pretty sure there is an address decoder on the PowerCache itself that takes care of only caching things that should be cached.
That would make sense and those (or that) Daystar engineers were pretty good. Is there some mechanism by which the cache can tell whether the SE/30 is in 24 bit mode and the cacheable space is even smaller? Or are the hardware addresses to memory always the first GB, and the memory maps documented are logical addressing rather than actual hardware addresses.
The external enable signal does not exist on the socketed PowerCache which uses the same GAL set.
That is interesting to know. How have you confirmed that the GAL set is the same?
@trag the IIci is special as the memory controller in there can control an external cache. No other machine besides the IIsi has that capability. On the IIsi it needs external decoding logic that’s done by the GAL on the Daystar adapter.
If you take a close look at the SE/30 adapter that GAL is wired up different than on the IIsi adapter. Pin 19 of the GAL connects to /CENABLE. It is set to be low all the time in the fusemap. On the IIsi adapter /CENABLE connects to Pin 18 on that GAL which is only active if the memory controller in the IIsi wants to address an external cache.
Thank you for the information. Interesting, as always.
The memory controller on the IIci has some limited cache support/control ability, but I don't think it fully controls a cache, as all the caches I've seen for the IIci include some kind of programmable logic (or a big ASIC) which is probably handling BERR and such. Caches for the NuBus PowerMacs, on the other hand, seem to consist of just a TAG RAM and a regular SRAM (in the needed widths), suggesting that either the NuBus PM memory controller or the PPC601 has cache control logic actually on board.
The PCI Power Macs just seem to have two sets of distinct SRAM, neither of them TAG, suggesting that the comparators have been moved to either the PPC or the memory controller.
However, take the above with a grain of salt. That's my preliminary conclusions for a fairly rushed overview. I don't know when I'll ever actually trace connections.