After tracing out the boards the old nemesis Buried Traces has appeared.
The data and address busses are obvious, as are most of the support pins, but there's a bunch of signals I can't be certain of as I'm fairly sure they're repurposed from the EDO use.
These are the RAS and CAS lines, there are two RAS and 8 CAS lines, but an SGRAM implementation only has four chips, with two active at a time. However SGRAM has four extra lines for mask operations so I think these might be used for that instead, but it's not in Apple's documentation and I can't find any pinouts for the ATI Mach 64 VT series of chips.
So if someone with a bit of time and a multimeter could find where these pins connect to on the chips that would be amazing. I'm not fussed about format. On the SGRAM chips pin 1 is the leftmost pin on the bottom as aligned with the text and counted anticlockwise, but just drawing the connections is fine.
I'm grouping these in connector order - pin 69 should be on the back pin side of 9.
9. VOE0 - This should be the clock line, and it might be connected via a pull up resistor to pin 60 (TermPwr).
69. VOE1 - I suspect this is Clock Enable on SGRAM.
10. VWE0 - Write enable, this should be connected to two of the chips.
79. VWE1 - Write enable on the other two chips?
12. VRAS0 - This should be RAS on two of the chips.
72. VRAS1 - Should be RAS on the other two chips.
13, 73, 14, 74, 15, 75, 17 and 77 - VCAS0-7. I think two of these will be used as CAS for the SGRAM and four of them as mask data for bulk operations.
Unfortunately unless I can find one of these rare modules or memory bus documentation for the Mach64 VT2 I can't be sure of the routing. I find any instances of the VT2 on a discrete card using SGRAM, though the VT4 did have one card. The documentation I can find suggests these chipsets have the same pinout but I can't find any actual documentation on this.
The data and address busses are obvious, as are most of the support pins, but there's a bunch of signals I can't be certain of as I'm fairly sure they're repurposed from the EDO use.
These are the RAS and CAS lines, there are two RAS and 8 CAS lines, but an SGRAM implementation only has four chips, with two active at a time. However SGRAM has four extra lines for mask operations so I think these might be used for that instead, but it's not in Apple's documentation and I can't find any pinouts for the ATI Mach 64 VT series of chips.
So if someone with a bit of time and a multimeter could find where these pins connect to on the chips that would be amazing. I'm not fussed about format. On the SGRAM chips pin 1 is the leftmost pin on the bottom as aligned with the text and counted anticlockwise, but just drawing the connections is fine.
I'm grouping these in connector order - pin 69 should be on the back pin side of 9.
9. VOE0 - This should be the clock line, and it might be connected via a pull up resistor to pin 60 (TermPwr).
69. VOE1 - I suspect this is Clock Enable on SGRAM.
10. VWE0 - Write enable, this should be connected to two of the chips.
79. VWE1 - Write enable on the other two chips?
12. VRAS0 - This should be RAS on two of the chips.
72. VRAS1 - Should be RAS on the other two chips.
13, 73, 14, 74, 15, 75, 17 and 77 - VCAS0-7. I think two of these will be used as CAS for the SGRAM and four of them as mask data for bulk operations.
Unfortunately unless I can find one of these rare modules or memory bus documentation for the Mach64 VT2 I can't be sure of the routing. I find any instances of the VT2 on a discrete card using SGRAM, though the VT4 did have one card. The documentation I can find suggests these chipsets have the same pinout but I can't find any actual documentation on this.
