According to some old MacTech article, there's
no theoretical limit on the L2 cache size for the NuBus PowerMacs. Which seems plausible, if the cache embarks all the required memory and logic (tag, comparison logic, ...) to answer the CPU request (later systems would rely on the tag and comparison logic being part of the system controller and so limited in size to whatever those can handle; of course even later the L2 would migrate to the CPU itself).
Edit; from the readable chips in
@ymk picture...
MCM6206 are SRAMs (32kx8)
74FCT521 ares 8-Bit Identity Comparator
74FC244 are buffers/line drivers
PI5C3257W is a Multiplexer/demultiplexer Bus Switch
And a couple of PALs
So I suppose the first part of the picture is the controller part and contains everything but the actual cache SRAMs
TC558128AJ are 128kx8 SRAMs, so the second part of the picture contains the actual 1MiB of cache SRAMs
Would be interesting to figure out the details of the wiring and PALs content. In addition to duplicate that 1 MiB module, it could theoretically be possible to design an even larger one by having more data SRAM, more tag SRAM, and larger comparators (though it would probably be prohibitively costly vs. the expected performance gain).