bigmessowires
Well-known member
Hi! I'm seeking any and all details about the memory controller on the 128K, 512K, and Plus. This was some custom circuitry implemented in PALs that facilitated sharing of RAM between the 68000 and the video circuitry. I know the basic principle was that when the video circuitry was accessing RAM to fetch pixel data, the CPU was somehow made to wait. But that's about all I know.
How exactly was the CPU made to wait?
How exactly was time divided between the CPU and the video circuitry?
How were CPU bus cycles kept synchronized with the time division pattern?
How were the CPU address and data busses isolated from the RAM?
I've looked at the Mac 512K schematics, but they don't really answer my questions. For example, I see a pair of LS244's at locations 12E and 13E used to drive RAM data onto the CPU data bus, but nothing that drives data in the opposite direction, which would be necessary for CPU writes to RAM.
In the absence of details on the original memory controller, I've attempted to design my own for my Plus Too project (a hardware clone of the Mac 128K, 512K, and Plus). You can read about my memory controller design here. Any feedback you have on the design is very welcome!
How exactly was the CPU made to wait?
How exactly was time divided between the CPU and the video circuitry?
How were CPU bus cycles kept synchronized with the time division pattern?
How were the CPU address and data busses isolated from the RAM?
I've looked at the Mac 512K schematics, but they don't really answer my questions. For example, I see a pair of LS244's at locations 12E and 13E used to drive RAM data onto the CPU data bus, but nothing that drives data in the opposite direction, which would be necessary for CPU writes to RAM.
In the absence of details on the original memory controller, I've attempted to design my own for my Plus Too project (a hardware clone of the Mac 128K, 512K, and Plus). You can read about my memory controller design here. Any feedback you have on the design is very welcome!