Maybe you'll have to start calling me the CPLD whisperer... then again, maybe not. Either way:
Introducing... TashMachine!
Elevator Pitch
It's a behavioral clone of the Integrated Woz Machine, the ASIC that acts as the floppy controller in the Mac (and the Apple IIgs and IIc+, maybe others?), written in Verilog and sized to fit in an Atmel/Microchip ATF1508 CPLD.
Project Status
Showing first signs of life. It is able to boot the ITXPlus from a Floppy Emu. Much testing (and probably debugging) remains to be done.
Caveats
At the moment, the biggest point of bother is that what caused the code to go from nonfunctional to functional was... changing what signal was routed to an extra output pin for debug purposes. That means that something somewhere in the code is marginal and that's bad. The ATF150x CPLDs (or at least their associated toolchains) are kind of temperamental in this way, just ask @zigzagjoe.
What's Next
Well, I need to figure out the Heisenbug that I earlier mentioned, but I'm not exactly sure how to go about it. This is my first non-trivial Verilog/HDL project, and the tools I'm using aren't the sharpest ones out there. For those interested, I'm using an ancient version of Quartus II to synthesize the HDL code for a discontinued Altera CPLD and then using an Atmel/Microchip program called POF2JED to convert the output of Quartus II for use in an ATF1508. Extra pins are about as far as my debug capabilities go, and if those can't be relied on, well...
Cursed Testing Environment Photo

Not pictured: USB extension lead stretched across the desk to my workstation for the Bus Pirate that I'm using for JTAG.
Code
Soon...
Introducing... TashMachine!
Elevator Pitch
It's a behavioral clone of the Integrated Woz Machine, the ASIC that acts as the floppy controller in the Mac (and the Apple IIgs and IIc+, maybe others?), written in Verilog and sized to fit in an Atmel/Microchip ATF1508 CPLD.
Project Status
Showing first signs of life. It is able to boot the ITXPlus from a Floppy Emu. Much testing (and probably debugging) remains to be done.
Caveats
At the moment, the biggest point of bother is that what caused the code to go from nonfunctional to functional was... changing what signal was routed to an extra output pin for debug purposes. That means that something somewhere in the code is marginal and that's bad. The ATF150x CPLDs (or at least their associated toolchains) are kind of temperamental in this way, just ask @zigzagjoe.
What's Next
Well, I need to figure out the Heisenbug that I earlier mentioned, but I'm not exactly sure how to go about it. This is my first non-trivial Verilog/HDL project, and the tools I'm using aren't the sharpest ones out there. For those interested, I'm using an ancient version of Quartus II to synthesize the HDL code for a discontinued Altera CPLD and then using an Atmel/Microchip program called POF2JED to convert the output of Quartus II for use in an ATF1508. Extra pins are about as far as my debug capabilities go, and if those can't be relied on, well...
Cursed Testing Environment Photo

Not pictured: USB extension lead stretched across the desk to my workstation for the Bus Pirate that I'm using for JTAG.
Code
Soon...

