Quadra dram configuration

[marmotta]

Hi

I have one Quadra 700 and Quadra 950... I'm already have four 16mb simm, but one is died! My 16mb simm is 8 chips, 60ns, and 2k refresh. If I buy another simm with 8 chips, 60ns, but is 4k refresh.... is a problem?

The ram controller of Q950 and Q700 accept 4k refresh sticks? If I mix 2k and 4k, all simm go at 4k?

30pin, 2k refresh, 16mb simm is very hard to find.... 

 

[trag]

I'm already have four 16mb simm, but one is died! My 16mb simm is 8 chips, 60ns, and 2k refresh. If I buy another simm with 8 chips, 60ns, but is 4k refresh.... is a problem?

All 30 pin 16 MB SIMMs are 4k refresh. If you have one labeled 2k, it is either mislabeled or it is not 16 MB or it is not a standard 30 pin SIMM.

Refresh occurs by row address. A 12 bit row address gives 4k refresh. There are only 12 address bits available on 30 pin SIMMs.

In order to be 2k refresh, a 30 pin SIMM would only have 11 row address bits. The column address cannot be greater than 12, because there are only 12 address bits availabe. 11 row address bits and 12 column address bits is 23 address bits total, which cannot address 16MB; they can only address 8MB.

On 30 pin SIMMs, both the row and column address must be 12 bits in order to provide 24 bits (16MB) of address space and hence the refresh is always 4k.

 

[marmotta]

Good! But I have searched the code on the my dram chips, on one simm I have this code: HY5117400B and by my search is 2k refresh. Others simm is different and use this chips: IBM 0116400BJ1D In theory is 4k... I have the simm already mixed?    

 

[trag]

That HY5117400B is 4M X 4. Eight of those would in theory make a 16MB SIMM, but only with some additional logic to convert upper address bits into chip enables. The problem is those chips don't have 16M addresses, only 4M addresses, so two chips must be the lower 4M addresses, then two different chips must cover 4M to 8M, then two more chips 8M to 12M etc.

This is what is called a composite SIMM. I don't know how the refresh will look to the host system. It might work in concert with non- composite SIMMs but generally, composite SIMMs should be avoided on Apple systems.

 

[marmotta]

Thanks for the info!  :beige:

In my quadra 950 he was present two simm of IBM 0116400BJ1D, one simm HY5117400B, and one Panasonic MN4117400BSJ-06. All simm have same aspect and have parity chip, work good together, before HY5117400B died...   

Now I can suppose if possible to use two simm of IBM (4k with parity) with two other simm without parity and already 4k, true?

 

[yuhong]

Yes, the chips on 16MB 30-pin SIMMs are supposed to be 16Mx1. To use 4Mx4 chips would require extra logic. These SIMMs was never very popular for several reasons (including early 16Mbit chips being expensive and 400mil). I wonder which kinds of addressing the 512KB/2MB/8MB SIMMs with PALs uses.