Not sure how delay lines double frequencies. Thats one thing I never personally ever saw. But that can explain the DS1013M delay ICs I have just recently seen in a 68K based graphics generator board.
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MicroMac Performer SE Mod
- Thread starter Busterswt
- Start date
Nevermind. Power of google. Wow, I never knew such a thing existed. Any time I needed to double or multiply frequencies, I just used a PLL with a divider in the feedback loop. Hmm learn something new everyday.
Sadly from what I see on google, an XOR multiplier requires a delay to be exactly half of the half-period so it can be 90 degrees out of phase. So if the clock changes in frequency, it will shift the duty cycle, but that is a cool way to make a frequency to PWM converter.
Sadly from what I see on google, an XOR multiplier requires a delay to be exactly half of the half-period so it can be 90 degrees out of phase. So if the clock changes in frequency, it will shift the duty cycle, but that is a cool way to make a frequency to PWM converter.
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According to some of the articles I found, it was mentioned never to use this circuit design. Probably why have never heard of it.
So you dont need a GAL here. Just use a clock multiplier IC and form a small circuit around it. Like this one:
https://www.jameco.com/webapp/wcs/stores/servlet/ProductDisplay?catalogId=10001&langId=-1&freeText=pll-clock-multiplier&storeId=10001&productId=2054361&krypto=4We6orF%2FQq5lWZdXyYEvrdAYAdhOJj8HYljOOKxHoLoVxQzggZZcSX2XGmFUnAG0lQR7Dh4ZNJ0lR8bZ3KHdN3xKnbBF4dPsto26knu2gUY%3D&ddkey=https%3AStoreCatalogDrillDownView
So you dont need a GAL here. Just use a clock multiplier IC and form a small circuit around it. Like this one:
https://www.jameco.com/webapp/wcs/stores/servlet/ProductDisplay?catalogId=10001&langId=-1&freeText=pll-clock-multiplier&storeId=10001&productId=2054361&krypto=4We6orF%2FQq5lWZdXyYEvrdAYAdhOJj8HYljOOKxHoLoVxQzggZZcSX2XGmFUnAG0lQR7Dh4ZNJ0lR8bZ3KHdN3xKnbBF4dPsto26knu2gUY%3D&ddkey=https%3AStoreCatalogDrillDownView
Correction: 68030 E1 CLK is driven by U5, not U6 as misstated above.
I/CLK - Pin 1 of U7 is a 25MHz input from the onboard crystal can. It's the only GAL connected to all three clocks when installed in an SE, at which point the GAL itself becomes superfluous. Strange thing is that the 16MHz clock input for the 68030 on my Plus version buzzed out to be an output from U5 at pin 19 - I/O/Q and not from U7?
U4 is driven by the 25MHz can on Pin 1 - I/CLK - and has 8MHz on Pin 3 - I - just like U7.
U3 appears to run with 25MHz on Pin 1 - I/CLK - with no other clock connected.
U5 is connected to 8MHz on Pin 1 - I/CLK
U6 is connected to 8MHz on Pin 1 - I/CLK
Unconfirmed(?) clock diagram posted above.
I'll definitely recheck the clocks, just pulled the Performer/Plus out and it's sitting on printouts I did tonight from the redux thread. I've got a couple of days off so I'll try to finish off my coloring book's p.5 which is of course, U7! :
I/CLK - Pin 1 of U7 is a 25MHz input from the onboard crystal can. It's the only GAL connected to all three clocks when installed in an SE, at which point the GAL itself becomes superfluous. Strange thing is that the 16MHz clock input for the 68030 on my Plus version buzzed out to be an output from U5 at pin 19 - I/O/Q and not from U7?
U4 is driven by the 25MHz can on Pin 1 - I/CLK - and has 8MHz on Pin 3 - I - just like U7.
U3 appears to run with 25MHz on Pin 1 - I/CLK - with no other clock connected.
U5 is connected to 8MHz on Pin 1 - I/CLK
U6 is connected to 8MHz on Pin 1 - I/CLK
Unconfirmed(?) clock diagram posted above.
I'll definitely recheck the clocks, just pulled the Performer/Plus out and it's sitting on printouts I did tonight from the redux thread. I've got a couple of days off so I'll try to finish off my coloring book's p.5 which is of course, U7! :
@techknight how might the interaction between U7's 25MHz clock input and 8MHz on a general purpose input fit into your models of frequency manipulation?
How do the 25MHz and 8MHz clocks synchronize?
How do the 25MHz and 8MHz clocks synchronize?
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For a quick test you could just hook up a jumper wire to get C16M onto the accelerator and see if that brings it to life.
Another question is, is the 030 supposed to run at 16MHz at all or is it made to go 25MHz? Looks like it is after seeing your last post jt.
Nevertheless 16MHz is needed for everything to work and that has to be generated somewhere.
Another question is, is the 030 supposed to run at 16MHz at all or is it made to go 25MHz? Looks like it is after seeing your last post jt.
Nevertheless 16MHz is needed for everything to work and that has to be generated somewhere.
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I haven't looked to see if the Performer was offered in faster versions, but I've long had a sneaking suspicion that it was designed to do just that.
I got confused by the black magic of frequency manipulation when I saw my first clip-on overclocking kit. Is 8MHz added to 25MHz to get 33MHz and then stepped down to 16MHz? If the incantation for magic be done in that manner, the Performer could theoretically run at 33MHz as well as 25MHz? :blink:
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If they are generated separately, They dont. One has to generate the other, and they lock by phase, thats it.
Well, that was a silly thought I had last night. It was late and I was 33MHz makes no sense while 25MHz does.
View attachment 21530
U5 may not be driving 68030 CLK at all, it may only be tied the E1 pin on the 68030 that would be being driven by a U7 output when in 16MHz mode. In 25MHz mode its primary I/CLK input of U5 would be engaged to U3 an U4 . Haven't got coloring book p.4 vor U6 diagrammed in AI, which probably means I never finished buzzing a/o verified my mapping of it. That leaves a couple of possibilities. U6 along with U5 are tied to the 68000 CLK at 8MHz with U5 determining the 68030 CLK state and throttling a natively 25MHz system down to 16MHz? U6 may or may not require the Performer's system clock, merely relaying 68000 signals to the overall 25MHz system?
Dunno, morning musing WAGs all around based on fuzzy imagery of the flow in the diagram above.
View attachment 21530
U5 may not be driving 68030 CLK at all, it may only be tied the E1 pin on the 68030 that would be being driven by a U7 output when in 16MHz mode. In 25MHz mode its primary I/CLK input of U5 would be engaged to U3 an U4 . Haven't got coloring book p.4 vor U6 diagrammed in AI, which probably means I never finished buzzing a/o verified my mapping of it. That leaves a couple of possibilities. U6 along with U5 are tied to the 68000 CLK at 8MHz with U5 determining the 68030 CLK state and throttling a natively 25MHz system down to 16MHz? U6 may or may not require the Performer's system clock, merely relaying 68000 signals to the overall 25MHz system?
Dunno, morning musing WAGs all around based on fuzzy imagery of the flow in the diagram above.
8 goes into 32, but not 33 or 25. Not sure how they can get 8 from either of those. It would require a PLL.
Heh, you caught me proofing that post. If I understand you at all . . . that would mean the Performer logic is natively a 25MHz system running off its crystal can. The 8MHz GALs interact with the 68000 on its clock and relay addressing, data and control signals to the 25MHz system?
Dunno, I'm going with the fuzzy flow over coffee ATM. I'll buzz the clock lines later when it kicks in and higher functions come online.
edit: caught me ready to pull the trigger on this one!
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68K communication is asynchronous by nature. it could run at 500Mhz and the bus at 8Mhz, it wouldn't matter. You would have a shit ton of wait states but it would work.
The catch is the E/VPA/VMA of the synchronous bus. It would need to be locked to the system bus if the system uses these, and the Mac does. the VIA, etc use it. So there would be PALs/GALs that interface with this, and thats that.
The catch is the E/VPA/VMA of the synchronous bus. It would need to be locked to the system bus if the system uses these, and the Mac does. the VIA, etc use it. So there would be PALs/GALs that interface with this, and thats that.
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Ouch, you just hurt my brain.
Yea I know. It took me awhile to figure it out, but once I did I began to understand it. I needed to if the RAM card was ever gonna work.
:lol: You have no idea how much better you just made me feel about my obvious shortcomings!
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. . . that would mean the Performer logic is natively a 25MHz system running off its crystal can. The 8MHz GALs interact with the 68000 on its clock and relay addressing, data and control signals to the 25MHz system?
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Does that jibe with your models?
_____________________________________________________________________ post above _________________________
. . . that would mean the Performer logic is natively a 25MHz system running off its crystal can. The 8MHz GALs interact with the 68000 on its clock and relay addressing, data and control signals to the 25MHz system?
___________________________________________________________________________________________________________
Does that jibe with your models?
Without seeing the schematic and the GALs actual native boolean logic, its just a blindfolded shooting match guessing game.
The GALS functions are basically to emulate the E/VPA/VMA system, maybe some simple address decoding for a DeclROM, and the bus master takeover, using the Bus Grant, Granted to take over the 68000 before it will release the 030 from running.
The GALS functions are basically to emulate the E/VPA/VMA system, maybe some simple address decoding for a DeclROM, and the bus master takeover, using the Bus Grant, Granted to take over the 68000 before it will release the 030 from running.
@Trash80toHP_Mini I’ve got family in town, and limited time to work on this while they’re here. Working on buzzing out connections to compare to what you have done so far and maybe fill in the blanks. Almost done with U3; it’s a busy one!
What are the chances these GALs have had their fuses blown? Pretty good, I suppose?
What are the chances these GALs have had their fuses blown? Pretty good, I suppose?
Cool! I don't understand schematics or GAL formulas, but the Jesuits locked logic down tight at an impressionable age. Visualization of VLSI textbook imagery as roadmaps got locked down around second grade. I'll have to take another look at the GAL formulas in the ProtoCache threads again to see if I can wrap my head around this stuff. I've all but given up on ever thinking in terms of conventional schematics.
"Blindfolded shooting match guessing game" describes exactly what I do.
That's wonderful, got back from visiting the rug rat over Christmas.
If you have a chance, starting at the other end with the U7 pads would be the first thing to do. I can insert headers into the PDS thruholes for dragging the continuity tester, but dragging your soldered pins from the naked pads would be far less error prone. I'll work it from the GAL to the rest of the Performer. Extremely curious about how the 68030 CLK line wends its way through my roadmap of the Performer.
Chances would be near infinity to zed.
edit: merry 7th day of Christmas all! I'll switch back to a static avatar after the feast of the three wise guys. [
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