MDD Cache speed

indibil

6502
Hi, I've been trying to view the cache speed on my 2x1.42GHz MDD with OS9 and Gauge Pro, but it doesn't show any information about either L2 or L3. I can't find any app that gives me this information.

Is there a version of Gauge Pro for OSX? Or what app could show me the L3 cache speed, or at least the ratio?

I've been told it's in a register called L3CR, but I don't know how to access this register.

Thanks.
 
Try PowerLogix CPU Director? There's a Mac OS 9 version and versions for some earlier versions of Mac OS X.

Performance Tools/CHUD/Hardware Tools has a program called "Reggie SE.app" which lets you view registers.
 
Thanks for your help. I finally found a version of CPU Director that showed this information in the MDD under OS9, and it wasn't the latest version.

I verified that the cache ratio was 6:1, and the cache chips support up to 300MHz, so I decided to change the ratio to 5:1 by modifying the EEPROM. I've summarized it here:

https://rosysumenteinquieta.blogspot.com/2025/07/acelerar-la-cache-en-un-g4-mdd-dual.html

IMG_20250706_082129.jpg

IMG_20250706_103722.jpg

I hope with this information we can change the cache ratios as we wish.
 
I finally found a version of CPU Director that showed this information in the MDD under OS9, and it wasn't the latest version.
Do you mean the latest version doesn't run in Mac OS 9 (i.e. it's for Mac OS X) or that the latest version that runs in Mac OS 9 did not show the information? What are the versions that didn't work and the versions that did?
 
Do you mean the latest version doesn't run in Mac OS 9 (i.e. it's for Mac OS X) or that the latest version that runs in Mac OS 9 did not show the information? What are the versions that didn't work and the versions that did?
Under OS9 only the CPU_Director_1.5f5 version worked for me, the others gave me an error when opening the application.
 
I think your AI assistant may have just gotten really lucky. This is awesome that you found the correct byte and checksum information though! The reference for the 7450 series L3 Cache Control Register (L3CR) information can be found in section 2.2.5.5.15 of the MPC7450 RISC Microprocessor Family Reference Manual, Rev. 5. Bits 6-8 of that register (L3CLK) determine the cache frequency divider ratio. A hex "61" in that location gives you "0110 0001" in binary. A hex "51" in that location gives you "0101 0001" in that location. A ÷ 6 ratio needs "000" though and the only location that occurs doesn't change. ÷ 5 is "111" which doesn't appear at all. I also don't see how this could represent the ÷ 3.5 or ÷ 2.5 ratios that the CPU supports (could just be unimplemented. So something else may be reading the contents of this EEPROM and using its own logic based on what it finds to set the ratio which may or may not follow the assumptions that AI made. I'd be really interested in seeing what other values do here. If you have 300MHz cache chips, you can probably push them to ~330-350MHz before things get too unstable. 1.42GHz at ÷ 4 might be pushing it, but I bet 1.25GHz at ÷ 4 would work.
 
Back
Top