Anyone up for some IIcx troubleshooting assistance? We have clocks but no activity...

[Sideburn]

BDEN and CBREQ go low and then high on reset

 

[Sideburn]

Good point. Got distracted by the lack of sound chips.

4.75v onn VCC of the 030
15.62 mhm clock at E1

 

[Sideburn]

Thats good, the VIA is telling the GLU to overlay the ROM.

It should go to pin 49 of the GLU chip. Does that have continuity to the top of the pin?

What should go to pin 49? Sorry missed that part

 

[Sideburn]

UG11 and UF11 are slightly warm

 

[Phipli]

What should go to pin 49? Sorry missed that part

The overlay signal from via1, pin 6...

But, one thing at a time. @GRudolf94 is troubleshooting the CPU. Which is likely closer to an issue.

 

[Sideburn]

Thats good, the VIA is telling the GLU to overlay the ROM.

It should go to pin 49 of the GLU chip. Does that have continuity to the top of the pin?

ohh pin 6 to 49...

 

[Sideburn]

ohh pin 6 to 49...

Yes it has continuity

 

[Phipli]

Yes it has continuity

Then if the GLU is working, it knows that the ROM is needed and has it ready at the bottom of memory for the processor to start executing the boot process...

Probably best to concentrate on why the CPU isn't running.

 

[GRudolf94]

@Sideburn check /BERR and /HALT. Most other things seem to be okay-ish. DBEN is the Databus Buffer Enable, CBREQ is cache control and we don't care much about it atm.

 

[Sideburn]

@Sideburn check /BERR and /HALT. Most other things seem to be okay-ish. DBEN is the Databus Buffer Enable, CBREQ is cache control and we don't care much about it atm.

BERR and HALT are stuck high and stay there on reset.

 

[GRudolf94]

Okay. Lemme see what else then. The mental picture I'm building is a weird one, in which the CPU seems to just be running nonstop reading from ever-increasing addresses without actually doing anything...

 

[Sideburn]

Okay. Lemme see what else then. The mental picture I'm building is a weird one, in which the CPU seems to just be running nonstop reading from ever-increasing addresses without actually doing anything...

as well as R/W, DS, AS, DSACK...

 

[Phipli]

Okay. Lemme see what else then. The mental picture I'm building is a weird one, in which the CPU seems to just be running nonstop reading from ever-increasing addresses without actually doing anything...

Tristate buffers?

Is the bus even tristated on a cx??

 

[GRudolf94]

Tristate buffers?

It's one of the things I'm thinking

 

[Sideburn]

There are some signs of life as i mentioned with the address lines going high/low and BDEN, CBREQ even though they aren't important at least the cpu is doing "something"...

 

[GRudolf94]

Yeah, we just wanted to establish that it's actually doing something and those are not just spasms. Broken silicon sometimes still reacts in ways that could be interpreted as life.

 

[Sideburn]

There are no sims on the board is that ok? Heres a photo so you can get a visual of what were working with:

 

[GRudolf94]

No SIMMs is fine - if all else was well, the ROM code would still execute and go thru basic steps and try to size memory and annoyedly chime at you for having no memory.

 

[Sideburn]

No SIMMs is fine - if all else was well, the ROM code would still execute and go thru basic steps and try to size memory and annoyedly chime at you for having no memory.

Thats what i figured and bare minimum would be ideal for now.

 

[Phipli]

Thats what i figured and bare minimum would be ideal for now.

How... are you checking if it is booting?