I got your good news and your bad news kind of situation here:
Bad news: It's looking to me like we've got to reverse engineer the function of the PowerCache Adapter chip to get the LC NIC to work.
I started out mapping the similarities between the IIsi/SE/30 and the LC Slot NIC and hit a brick wall, so I attacked it from the other side. I've restarted the Rosetta Stone project, couldn't find the spreadsheet, so I'm working it out visually, before I try to locate or rebuild that crazy piece of work.
Good news: It's looking to me like we've got to reverse engineer the function of the PowerCache Adapter chip to get the LC NIC to work. [
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The IIci Cache Slot is the key to understanding the differences between Apple's several incompatible variations on the 68030 PDS theme. The machine specific PowerCache PDS adaptations for their IIci Cache Slot Accelerators provide clues as to the differences between these PDS implementations.
I've haven't got a PowerCache Adapter for either machine in question, but I do have one for the LCIII. Since it looks like it's pretty much a straight thru (right angled and flip flopped as it may be) PDS shoehorn with no active components on board, the LCIII's PDS looks to be as similar to the IIci Cache Slot as anything I've seen:
There are only seven tiny SMT resistors on board, eight of the same package type, but capacitors and then five large SMT capacitors that I'm guessing condition the power translation from the five power lines (only three of which are +5V pins, BTW) in the LCIII slot to the eleven Vcc connections on the IIci Slot/PowerCache Receptacle.
That's a total of just twenty capacitors and resistors needed to turn an LCIII slot into a PowerCache/IIci Cache Slot!
Once we've figured that control line translation stuff out it'll be lots of fun designing all manner of crazy adapter concoctions for PowerCache accelerated IIsi/SE/30 boxen. [}
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