Synchr030/S 256MB SDRAM Accelerator for the SE/30

[ymk]

Synchr030/S is a 256MB SDRAM accelerator PDS card for the Macintosh SE/30. It combines a custom memory controller with 256MB of SDRAM to double the SE/30's memory capacity and throughput. There's no longer a need to deal with broken SIMM slot tabs, dodgy contacts or aging SIMMs. Synchr030/S provides fastest possible 2-cycle reads and writes to the 68030 CPU, making it the performance equivalent of a 256MB L2 cache that never misses.





To enable 2-cycle reads, installation of the included /ECS Tap PCB is required. This small board fits over the CPU pins on the back of the logic board and routes the CPU's /ECS signal to the PDS card. This signal is not present in the SE/30's PDS connector:

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A System 6/7 extension enables fast 2-cycle access to SDRAM and expansion to 256MB under System 7 with a IIsi-derived ROM, such as the Rominator II. The extension also performs ROM shadowing, which relocates ROM-resident Toolbox routines to SDRAM, where they can execute faster. Without the extension, the card operates as 128MB of DRAM with the stock 4-cycle access time.

​

The controller operates at 63MHz, providing a 32-bit data path to memory at a maximum throughput of 31.33MB/s. Unlike the stock DRAM controller, Synchr030/S does not stall for refresh cycles, so consistent access times are guaranteed. All signals through the card are unbuffered, routed directly to the PDS passthrough connector. The two large capacitors on the board are polymer and will not leak.

Connectix Maxima is supported under System 7, which enables large, disk-backed RAM disks. SDRAM-based RAM disks typically yield 4.5MB/s with the stock CPU, faster than any SCSI device.

/STERM and /DSACK signaling options are selectable via jumper for compatibility with CPU accelerators. Compatibility is confirmed with @zigzagjoe's Interware Booster 50-SE30F clone (with /DSACK) and @Bolle's PowerCache P33 (with /STERM). Both of these accelerators benefit significantly when paired with Synchr030/S.

On the rear of the PCB, three LEDs indicate various conditions. These are visible through the SE/30's frame, and MacEffects clear case:

• "ACCEL" LED (emerald): Indicates fast 2-cycle SDRAM access, after the extension is loaded.
• "/ECS" LED (white): Indicates activity on the stock CPU's /ECS signal. Will be off when a CPU accelerator card is in use, even if connected to the logic board.
• "FPU" LED (yellow): Indicates floating point unit access. This indicator is mirrored at the "FPU LED" through holes at the upper right corner of the PCB. An external LED header may be soldered here if desired. No resistor is needed.

MacBench 3.0 Results:



Performance summary:

MacBench 3.0 CPU score: +24%
Apple Personal Diagnostics 1.1.1 memory bandwidth: +70%


Specifications:

Power consumption: 0.43A @ 5V (2.15W) typical
Capacity: 256MB
Bandwidth: 31.33MB/s R/W
Clock speed: 62.66MHz
Slot space: C, D
Connections: SE/30 PDS male and female, expansion port, FPU LED
Weight: 123g
PCB construction: Eight layer, ENIG


Note:

• CPU accelerators may be sensitive to placement in the PDS chain.
• BMOW or other IIsi-derived ROM is required to enable 256MB under System 7.
• Basic soldering skills required for installation.

Special thanks for compatibility testing, accelerator insight and feedback:
@JDW @Bolle @zigzagjoe @maceffects

Synchr030/S by YMK Devices on Tindie

Synchr030/S is a 256MB SDRAM accelerator PDS card for the Macintosh SE/30.

www.tindie.com

 

[robin-fo]

Wow!

 

[joshc]

Incredible. Do you know if it will work with a socketed Daystar PowerCache 68030 @ 40/50MHz and an Asante MacCon Ethernet card in the passthrough PDS slot?

 

[ymk]

Incredible. Do you know if it will work with a socketed Daystar PowerCache 68030 @ 40/50MHz and an Asante MacCon Ethernet card in the passthrough PDS slot?

I do not. I expect the socketed PowerCache would work. If a card requires either slot C or D space, it will not work.

 

[nickpunt]

Very cool! What is the Expansion port for? And why did you choose that particular height for the passthrough PDS? Do you have any photos in a machine and how the placement might line up?

 

[ymk]

What is the Expansion port for?

Potential peripherals and GPIO that don't require the full bandwidth and complexity of PDS.

And why did you choose that particular height for the passthrough PDS?

It clears the drive cage without getting too close to the CRT.

@zigzagjoe's Booster clone is pictured here. To work in this configuration, it requires its CPUCLK line cut and jumped with 1.5KΩ+1nF in parallel.

 

[cheesestraws]

Now this is a cool and novel thing. Well done!

 

[Melkhior]

To enable 2-cycle reads, installation of the included /ECS Tap PCB is required

Mmm, I'm curious as to why /ECS is needed? 2-cycle is only possible with /STERM according to the documentation; while caches can't really do the tag lookup fast enough, they usually can do 2-cycle read by simply asserting /STERM immediately, and then forcing a bus retry if the tags don't match. So in theory, you should be able to do the same?
... though that's for async SRAM that will pick the address asynchronously. With SDRAM, you might need an early warning to catch an earlier edge on the clock?

I'd love to see the details of how the controller is implemented (I have though about doing something similar but embedded in a variant of the IIsiFPGA), but I believe this isn't an open-source design?

 

[ymk]

Now this is a cool and novel thing. Well done!

Thanks!

Mmm, I'm curious as to why /ECS is needed? 2-cycle is only possible with /STERM according to the documentation; while caches can't really do the tag lookup fast enough, they usually can do 2-cycle read by simply asserting /STERM immediately, and then forcing a bus retry if the tags don't match. So in theory, you should be able to do the same?

The card does use /STERM, but can also use /DSACK. /STERM is the proper setting with the stock CPU.

It's not just a matter of asserting /STERM in time, but having valid data ready. You mention caches can't do a tag lookup fast enough (which is typically SRAM), so pulling data from SDRAM in less time is a challenge. That's where /ECS is essential. A bus retry would incur a huge performance penalty and defeat the whole purpose. The logic on this card makes no connection to the signals needed for a bus retry.

Apple did include /ECS on the IIfx PDS, but on the SE/30, the signal is N/C. Without it connected, the card falls back to three cycle reads. You can see the impact of this on benchmarks (second vs third bars).

I'd love to see the details of how the controller is implemented (I have though about doing something similar but embedded in a variant of the IIsiFPGA), but I believe this isn't an open-source design?

It is not an open source design.

 

[olePigeon]

Could this design be adapted for the IIci?

 

[ymk]

Could this design be adapted for the IIci?

Not as is. Two cycle reads wouldn't be possible. Even the IIsi pushes the SDRAM beyond spec.

A design optimized for 25-33MHz machines would look very different.

The goal for this card was maximum performance with a 15.66MHz bus. 2-1-1-1 burst reads tested slower than straight 2-cycle reads, which is why it doesn't support burst transfers. When 2-cycle reads aren't an option at faster clock speeds, the next best option is likely 3-1-1-1 bursts; much faster than the IIci's stock 5-2-2-2 timing.

 

[Melkhior]

The goal for this card was maximum performance with a 15.66MHz bus. 2-1-1-1 burst reads tested slower than straight 2-cycle reads

So it turns out to be true... I've seen design documents from SRAM and/or tag ram manufacturers claiming 2-1-1-1 burst was less efficient than 2-2-2-2 for fast L2 cache, complete with an explanation of the '030 behavior w/ and w/o burst. I've always wondered whether that was totally legit (it did make sense), or if it was also related to the fact that the competition supported burst mode and they didn't... it's nice to have unbiased ocnfirmation.

 

[ymk]

claiming 2-1-1-1 burst was less efficient than 2-2-2-2

2-2-2-2 denotes a burst transfer and would be slower than 2-1-1-1.

By "straight 2-cycle", I meant a single bus operation that transfers one longword, without /CBACK asserted.

​

 

[Melkhior]

2-2-2-2 denotes a burst transfer and would be slower than 2-1-1-1.
By "straight 2-cycle", I meant a single bus operation that transfers one longword, without /CBACK asserted.

Sorry, ambiguous notation on my side. I also meant 2-1-1-1 burst vs. 2 non-burst, which for 4 words in a cache line translate at 5 cycles total vs. 8 cycles total done back-to-back. Doing 2-2-2-2 burst will always be slower than 2-1-1-1 burst, and would be slower than 2 non-burst repeated four times if the CPU must wait for the end of the transaction with the critical word (it should be the same if the critical word is first and the CPU doesn't need to wait, but the '030 apparently need to wait).

 

[ymk]

Doing 2-2-2-2 burst will always be slower than 2-1-1-1 burst, and would be slower than 2 non-burst repeated four times if the CPU must wait for the end of the transaction with the critical word (it should be the same if the critical word is first and the CPU doesn't need to wait, but the '030 apparently need to wait).

The 030 can fill one cache entry without filling the whole line. Single reads free up the bus after two cycles where a burst commits the bus for at least five.

 

[croissantking]

If it could be made to physically fit with an 040 upgrade, such as @zigzagjoe ’s socket carrera 040, would it provide a nice performance benefit?

 

[croissantking]

Actually, couldn’t it go on top of Bolle’s riser? And would it work?

 

[ymk]

If it could be made to physically fit with an 040 upgrade, such as @zigzagjoe ’s socket carrera 040, would it provide a nice performance benefit?

It most likely would, as long as the extension loads. In 24-bit mode, the extension operates on the 030 MMU directly, which probably won't work on an 040. The accelerator would also need to work with the BMOW ROM.

Actually, couldn’t it go on top of Bolle’s riser? And would it work?

Mechanically, it fits, though it places the card very close to the flyback wire, so shielding would be needed. However, starting up with this configuration results in death chimes and simasimac. I don't know if there's a riser setting that would help.

 

[zigzagjoe]

The Carrera requires 32 bit, so OK there, however I doubt that any custom tweaks to the 030 mmu for rom shadowing would survive the transition to the 040. Probably would work as just RAM though, and caches would mitigate the lack of rom shadowing anyways.

Riser buffer the clock like my later booster pds cards do. Can't recall which Rev booster you have. The buffering does introduce a 5-10ns delay.

 

[ymk]

Shadowing in 32-bit mode doesn't modify the MMU tables. My Booster PCB says V1.2.