With my SE/30 out of commission until I can find replace whatever went bang in its power supply, I thought I'd turn my attentions towards the long-neglected SE version of the ethernet card. My first attempt revealed a fairly glaring mistake in that I'd got the PDS connector pinout backwards, but after a bit of thinking, I realised that if I just installed the connector on the 'wrong' side of the board, it would work.
So I did that, and was immediately greeted with yet more timing issues
. Turns out that there's an intensely annoying incompatibility between the '68000-like' bus mode of the ENC624J600, and the actual 68000 bus: on a read cycle, the 68000 asserts its address and data strobes simultaneously, but the ENC624J600 datasheet specifies a minimum 1 nanosecond delay between the chip being selected (derived from /AS and the address bus), and a data strobe being asserted. And even though it's only a nanosecond, if that delay isn't there, reads return garbage.
Thankfully, my new toy (an HP 54503 oscilloscope, picked up broken for $40 from my local surplus place and fixed up over the weekend), was very helpful in figuring it all out. It's even got a 68000 in it as well!
On the SE/30 version, the propagation delay through my 3 GALs of glue logic meant that I'd included that delay by accident while trying to fix something else, but the simpler glue logic on the SE meant that everything happened all at once. I got around it by using a feedback pin on the GAL to essentially force an extra propagation delay before the data strobes are asserted, but that's going to complicate things a bit for my CPLD-based reimplementation of the design. I suppose for that kind of a short delay, just sticking a couple of inverters on the data-strobe lines might be enough to do the trick, but it's really annoying to have to do that!
In any case though, I've got something working, and after a few tweaks to the driver, we have functioning ethernet! The performance figures are interesting compared to the
results I got on the SE/30 - for small repetitive operations, it's fairly consistently a bit slower than half the speed of the SE/30, but for bulk data transfer it actually holds its own pretty well - not quite as fast of course, but surprisingly close given the slower CPU!
This was a really heartening pick-me-up. After all my frantic activity on this project for the past couple of months, I was starting to burn out and was struggling to find the motivation to keep working on it - especially before I realised that I could salvage my prototype SE card by mounting the PDS connector upside down.
There's still a ways to go - these prototype boards still have some major hardware bugs that I'm kludging around, and I really need to get on with that new hardware revision for both of them. Though I suppose I'd better fix my SE/30 first, so I have that machine available to test cards in. The joys of retrocomputing, eh?