So, the first question. Who wants to try out a replacement RTC that's pretty much ready to go?
https://github.com/quorten/macsehw/tree/385867165613ad08207191b636d70cf82b467505/firmware/rtc
Now, for the tech discussion. Unfortunately, I found out that the ATTiny85 does not have the hardware capabilities to use the 32k crystal as a timing reference while the core clock runs at 8 MHz. The only option to connect directly to a crystal and capacitor buffer circuit is via direct drive of the system clock. The 20-pin SOIC/TSSOP ATTiny87 does, however, have the necessary hardware features, but that would require an adapter circuit board.
In any case, given the hardware limitations of the ATTiny85, I believe I now developed a pretty solid firmware for it. The AVR clock is run at 8 MHz and a timer based off of the internally generated clock generates the 1-second interrupt signal. The crystal connection is not used at all, so the pins are set to pull-up inputs. This does mean that time drift will be a much bigger problem than usual.
Also, after thinking through things more from writing my automated test suite, I decided that triggering serial communication events on the falling edge may be more defensive programming than triggering on the rising edge... given the fact that I've seen mention that the ROM erroneously reads the output data just after the rising edge of the clock rather than just before like it is stated to in the Hardware Reference.
The automated test suite itself needs more work on how it handles timing with simavr... due to timing issues it can have intermittent failures when simulating at higher clock speeds. Another thing is that I'm almost done extending it so that it can also be used in physical hardware test, via Raspberry Pi. (Actually sysfs GPIO could be used to support any Linux board, though I personally don't like sysfs GPIO.)