The Mac II has separate CAS and RAS lines going to each SIMM. Does that mean that all the banks are getting refreshed independently? Or can I assume that while accesses may occur at different times, the CAS-before-RAS refresh will always be synchronized?
If they're completely independent, then I'll need to build the whole design 4 times, which would make it impractical to just use 74 series logic, and instead actually find a CPLD or FPGA and appropriate level shifting hardware (since all the ones I can find run at 3.3v).