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Farallon ETHERMAC LC NSC w/NuBus drivers in the SE/30 PDS?

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@maceffects Here's how to go about checking my wrap map and how to go about starting one for your SE Adapter. This one has been kicking around in my pocket:

 

Wrap-Map-HowTo.thumb.JPG.beff5c67140b3a4f502eccced73281e7.JPG

 

To create the map:

1 - Choose a pin location on the LC PDS' pinout grid, in this case Row 30 in column C is A19 (signal and coordinates highlighted in yellow)

2 - Identify C30 in the wrap map sheet in the center and mark it with a dot (also highlighted in yellow) Table is natively LC PDS format.

3 - Identify signal A19 on the 030 PDS and mark it with a dot

4 - Read off column and row location of A19 on the 030 PDS (highlighted in pink)

4 - A19 also happens to be in Column C on the 030 PDS, but it's on Row 29

5 - Go back to the dot at C30 on the wrap map and enter C29 (in pink here, pencil is editable)

 

To proofread/error check my new wrap map, work from the paired grid locations of the wrap map in the center. Read print at grid locations on LC and O30 sides, compare them to make sure the .TXT is identical on both sides.

 

Doesn't matter what the signal themselves are, just the .TXT string. It's maybe a bit like working backwards from One-Time Pad Code using DCaDftMF pinouts with an oddball offset table cypher twist to it? What goes into one side of the wrap map substitution table needs to come out in plain text on the other. The trick is to build the substitution key correctly so the wires can be plugged into the switchboard for proper communications between the two sides. I'm sure there's a far more simple explanation for the type of encoding this is, but that's the image that popped up in my head.

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I just knew I screwed it all up!

 

74LS04-Logic-Worksheet.thumb.jpg.6f704b17582e3ff6be9511154abd7585.jpg

 

This might be better. It would have parallel lines heading to the 030 this way, so I'd gate them to a single line with another jumper block. Still trying to get a handle on this so I've built a worksheet. The fluidic computing model in my head doesn't translate well at all to digital logic it would seem.

 

Any help from anywhere would be greatly appreciated. I'm sure Bolle's many projects keep him too busy for a primary ed course. Gotta see if I can grok the CMOS Cookbook on another pass. Would the earlier TTL Cookbook be better as a primer?

 

In Bolle's diagram, I just can't get the notion that the shunt is supporting a column of water in the inverter out of my head. :-/

 

Bildschirmfoto 2019-04-28 um 11.52.26.png

 

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Thanks, here's the finished first draft from yesterday. If you or anyone else could check it for errors using the instructions in the post above it would be much appreciated.

 

RoughWrapMap2.thumb.JPG.51a091368258eb35122ba31cc0b1a1f7.JPG

 

Here's what I'm planning for the Logic at this point. Not crazy about having two wires coming to the block from each address pin on the 030 PDS, but this is what I can do without adding another jumper block trio to neck it down to one wire:

 

LC-030-Logic-0-002.thumb.jpg.4449ed489d045fc5b5e4c9670e35768b.jpg

 

Thinking in .TXT:

 

First test:

No connections to 74LS04

Yellow from LC PDS address lines implemented

Light brown non-inverted signals implemented

All three jumpers completing the circuit

Expected result: HARD fail in this config, it will be overwriting Video Memory space in the SE/30 unless the video subsystem runs within  the high order bits? NIC uses A1-A16*****

 

Second test:

Unwrap the temporary (purposely left longer} wire for 030 PDS A22 from the jumper block, cut, re-strip and wrap it it to the header on the jumper block for Pin 8 Y4

-  at this point I could just direct connect the A22 lines for inversion on the 74LS04 socket as it will always need to be inverted? Food for thought.

If the card looks like it's starting to work in SlotID $A

-  I can put off messing with the other two address lines. They're there in reserve in the case that we need to implement the NIC in the NuBus Slot Space of the IIsi: SlotID $9.

 

Hail Mary:

Give up on $A and beat the snot outta every conceivable $9 setup, including variations on the /NUBUS signal of the 030 PDS.

 

 

Time for me to check the rough map as I transcribe it into the AI file. Little outside help with the error checking please?

 

 

 

edit: hrmmm ***** Video in Slot $E of the IIsi and the SE/30 use A1-A16 I've got another silly notion. If nothing else works, might it be possible to redirect addressing of the NIC to A17-A31 in the Slot $E space without conflict?

 

Edited by Trash80toHP_Mini

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Meh... went through DCADFTMF again.

We might need to decode some more address lines to generate the /FC3 signal that tells LCPDS cards the addressing mode.

I did not know about that one earlier, so our test card might still be doing 32bit addressing, it just didn't look like it does from just looking at the used address lines.

 

Maybe we will have to take a step back and test the card what mode it is using. If it is indeed running in 24bit mode only we are fine with what we got so far.

If it is switching modes we need to implement some logic to decode the 32bit address range and set the /FC3 bit accordingly so that the address decoder on the card can actually be fooled to generate a card select signal.

We will have to watch address bits from 20 to 31 to see what's going on.

 

This is what every LCPDS card should be doing:

 

1928855467_Bildschirmfoto2019-05-05um14_32_15.png.ab46923992af20a7ef0a44002ee54d37.png

 

We will have to run address lines 20 to 31 through a GAL and generate:

-A22 (inverted for 24bit mode)

-A26 (inverted for 32bit mode)

-/FC3 (for the address decoder on the LCPDS card to work)

 

 

We have to pick up on: (high to low - assuming slot A)

 

1111 1010 0000 for 32bit mode ->/FC3 high, A26 inverted, A22 normal

0000 0000 1010 for 24bit mode ->/FC3 low, A26 doesn't matter, A22 inverted

 

 

Gotta get my LC out of the basement and check if my Asante LCPDS NIC does mode switching or not.

Edited by Bolle

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Damn! I was wondering about FC3 not swinging in the breeze? If It's just the one signal, all is not necessarily lost.  Can I re-wrap my board with /FC3 hardwired for 24bit mode with  the SE/30 running in same? We should get a yea or nay on the adaptation before developing your decoding logic, no? I've got a tube of 20 pin thruhole GAL sockets I can wrap on hand when the time comes. I'll drill a row or three more holes for one on the edge of the perf before I start wrapping anything.

 

Silver lining to this cloud: you figured this out while I was sleeping. I was excited about using epoxy or superglue to set headers and socket in place to start wrapping today. They'd have been in the wrong place as well. Any chance we'll be using my new jumper block config for anything in the next step? I thought that one was pretty cool last night. :mellow:

 

I'v also got a 28 pin wire wrap socket or two on hand and some 35mm x 45mm breadboards with DS tape on the back I can stick to the perf board edge leaving my cleaned up section free and clear. I'll drill two or three more rows of holes on the edge to fit the GAL socket to the board with header blocks and DIP socket already in place. Will our three spare inverters be sufficient? 

 

Lemme know if the 24 bit gambit is worth pursuing and I'll just wrap the headers and socket in place.

Edited by Trash80toHP_Mini

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Hooked up the LA to the card in the LC... it looks like my Asante card is running in the same mode as the machine is set to with no mode switches when the card is accessed.

 

When in 24bit mode all I get are interrupt acknowledge cycles (FC0, FC1, FC2 -> 111) while A31 and /FC3 are high.

Lots of action on the select criteria for slot E in the 24bit range though.

 

So I would say if we stick to 24bit mode for now we should be cool (if your Farallon card/driver behaves the same way as my Asante seems to do)

Put /FC3 to ground and see what happens when wiring up the rest as planned before.

Edited by Bolle

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That's good news all around. Found the GAL sockets, no need to risk further stress on my the wrap by drilling any new holes in the board.

 

Headers-Inverter-GAL.thumb.JPG.d99e00bb37acbf80063c783cd2958d4f.JPG

 

Also, the two header strips I had prepped will work hooked up inline without any chance of cross wiring the jumpers. [:)]

 

edit: I think I'll test all the re-stripped wires for continuity from wrap to socket before I start. I can get the inverter setup done while somebody checks my new wrap map for errors. I feel better now that /FC3 won't be floating as NA/NC. I'll have to re-check, but for now the FPU.SEL line may need to be nailed down. I hate leaving anything floating.

 

Will 16Master and CLK16M be tied together for the SE/30. IIsi might be a different thing altogether if the NIC's running at CPU clock instead of the baseline 16MHz reference clock?

Edited by Trash80toHP_Mini

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I think I'll test all the re-stripped wires for continuity from re-stripped ends to connector before I start, better a fix now than later. I can get the inverter setup done while somebody checks my new wrap map for errors. I feel better now that /FC3 won't be floating as NA/NC. I'll have to re-check, but for now the FPU.SEL line may need to be nailed down? I hate leaving anything floating.

 

Will 16Master and CLK16M be tied together for the SE/30 test? IIsi might be a different thing altogether if the NIC's running at CPU clock instead of the baseline 16MHz reference clock?

Edited by Trash80toHP_Mini

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1 hour ago, Trash80toHP_Mini said:

Will 16Master and CLK16M be tied together for the SE/30 test?

 

They should be tied together on the SE/30 logicboard already.

 

 

This is how I would tie things together:

 

2132571532_Bildschirmfoto2019-05-05um18_40_53.thumb.png.0f89eab37f8b440600f9d470b146abec.png

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That would be good if only I were at all familiar with the language of schematics. Unless you're wedded to the three in a row header setup I'm sticking with the block of four wiring setup I came up with last night as it cuts the inverter completely out of circuit when it's not required. On top of that, I don't have room for the inline implementation if I'm going to leave room for the GAL socket AND I've already wrapped socket and headers to the board. ::)

 

LC-030-Logic-0-003.jpg

 

Pic is set up with jumpers configured as above.

 

Headers-Inverter-GAL.JPG

 

 

Dots of crazy glue gel won't hurt to stabilize the components will they? That I can clean off with solvent easily enough for the WireWrapTwo GAL modification when the time comes (crosses fingers) if needs be. Is cyanoacrylate gel conductive? Looks like LOCTITE 444 is the thing to use, there might be something nasty in the gel versions? Having that stuff rocking around when I'm trying to wrap the pins is a massive PITA!

 

That's good news about the clocks, I can tie each to a twin on the 030 PDS so neither is left floating and wrapping them point to point is simple as can be.

 

I've had nagging thoughts about how the 030 talks back to the NIC. Will the driver take care of everything? Is the inverter bi-directional?

 

I'm not giving the IIsi even a passing thought from now on: KISS

 

 

 

 

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I wouldn't call them nightmares or daymares, but as I'm waking up I have visions of wires and diodes hooked up to all six inverters on that IC dancing around in my head. Speaking of which, I'm on my way to the rental office and mailbox to pick up them up right now.

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I wish I'd started error checking the wrap map before I put in the wash. I was working from a copy of it that I made at work this afternoon when I picked up some paperwork. Found a notation I couldn't read and bolted to the washing machine to peel the dead sea scroll out of the pocket of my jeans. Prized it apart like the sodden disintegrating manuscript it was and it's drying now. Thankfully I had posted the pic of most of it above. Thought I'd posted a pic of the whole thing, OOPSIE!

 

Copy is all marked up and everything looks like it's good to go. Now to the AI input stage and one last proofread.

Edited by Trash80toHP_Mini

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LC-030-Worksheet-02-002.PDF

 

edit: Bolle, if you get a chance let me know which pins I should connect the LC PDS clocks to on the 030 PDS side. There are nice little blanks on the wrap map worksheet for me to fill in. I think I've got it from your schematic, but  .  .  .

 

I'm second guessing myself on this and everything else this weekend. Do I have the lines in and out of each of my three select blocks for the inverters reversed? :mellow:

Edited by Trash80toHP_Mini

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 @Bolle You'll love this. Couldn't find Loctite 444 on their website earlier so I just searched it directly. At $29 for a 20g Bottle I'm sticking with their Gel. Very carefully sticking bits together with teensy dots from one of the two 2g tubes I got for under $3. Works out to something like half the price of the real deal, but sounds a lot worse. I don't think I ever used more than a few grams out of a 20g bottle before it went bad. ::)

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Thanks so much. Mine came up straight board yellow, so I've entered the test into the map PDF above. Haven't had a chance to compare printed paper to paper scratch, but screen to paper came off well. Just waiting on word about need to flip the inputs to the inverter or not and I can get moving.

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Nah, just fold the new printout up by column and check it column by column against the scribbling. I'll be doing the same. We both came up roses on the real proofreading and I'll be triple checking as I wrap. Noodling out a set of jumpers so I can send either set of address lines to the inverters. I'll set the jumpers for it straight through and test the kluge in Slot $E in the SE/30 with the Video ROM pulled after I figure out where to tap that interrupt, a Pivot Card and external display per the original plan. The tidbits bit of VRAM might still be a problem in the SE/30. The board may just too stupid to forgo loading the registers for video output when the Video ROM (DeclROM) is pulled.

 

The IIsi will be next up  if the SE/30's more rudimentary video setup remains in conflict. When no sense lines from a monitor are detected, buffering of first Meg of memory doesn't happen for the Vampire setup. So the IIsi has a much clearer line of demarcation for the video subsystem and prospects for conflict would seem to be lessened if not totally eliminated. Dunno, that a guess, but not a WAG.

 

Dunno, gonna build the crate, kick the tires, light the fires and see if/how she taxis around on the tarmac for now. I can also test the initial take on inverter ploy with the signals coming from either direction. That should keep me busy until Bolle gets back into the same room as his logic analyzer.

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Seems like some bad news about testing in the SE/30 in Slot $E with the Video ROM pulled and the Pivot Card/external display:

 

uniserver's post of five years past:

Quote

2 - pulling the SE/30 onboard video rom does not give you any worth-while results… the computer still boots using the internal CRT anyways, even if the rom is not installed.
so the internal video would have to be disabled in other ways.

Edited by Trash80toHP_Mini

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@techknight had posted this earlier in the thread, gotta find his GS Card development thread for more info.

 

Quote

The SE/30 is hampered by that darned video hardware, as its clocked off the main system bus and it doesn't use its own clock.

 

Once you get it off the dependence of that on-board video, than anythings possible. The Simasimac we are all known and accustomed to is generated from the video RAM at its initial power-up state, before the VRAM is ever initialized by the mac itself.


I did notice the simasimac is different between the 2 different RAMs used.

 

 

This tidbit appears to affect two concurrent projects, this one for my proposed testing methodology. Looks like I need to risk killing one of my IIsi boards in my first shot at a recap. :mellow: Again, when the IIsi boots without detecting sense line encoding, buffering of the first Megabyte of system memory as blood sucked VRAM does not take place. I imagine the IIsi might be run headless? At any rate, a PDS card can then become the startup screen in a clean break from Slot $E operations as opposed the the bastardized setup of the SE/30 hybrid? Dunno, food for thought and yet another hurdle on the road to straight up testing of the WireWrap1 prototype adapter.

 

Morning confuzzlement of the day: One of my old threads has resurfaced and reminded me that adapting the 68000 PDS to 020 PDS for Video is a done dea andl and I have an adapter in hand for taking a whack at adapting an LC PDS NIC to Plus/SE/Classic:

 

ThunderCache - E-Machines 020 to 68000 Adapter - A.JPG

 

@Bolle has already explained probable function of the GAL on the adapter to make this possible.

 

 

< Tangent >

So the SE/30 appears to be hitting on internal video to display the :huh: icon at startup before INITs load and even before the Video ROM is polled? That makes sense regarding its odd designation. From my read, it's not a Declaration ROM per se in terms of the Slot Manager, being either a subset (superset?) of DeclROM function? This makes sense as the SE/30 sits at the fork in the road of Compact Mac development:

 

The SE/30 can be seen as a Color QuickDraw/NuBus architecture PDS hybrid from IIcs Sire and SE QuickdDaw PDS dam. The Classic, which is assumed to be the replacement the SE/30 in hardware comparisons, can then be seen as its purebred sibling, being a direct developed of the Compact Mac line that lived on for a bit in the Classic II The Color Classic in its bloated Compact form factor would be the SE/30's badly malformed offspring.

< Tangent >

 

Edited by Trash80toHP_Mini
Apparently I can no longer typel ;-/

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