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PowerLogix UltraCache 1MB UC1MB

I can't seem to find any specs on this particular cache card.

I can't get it to boot in my PowerWave, and I wonder if there's an issue with the speed of the cache or what. The only quasi-spec related piece of info I got was from an issue of MacAddict which classifies it as a "high speed" cache for all Power Mac models.

An old MacQuake spec chart with a 3dfx card shows 128 mb ram minimum, a 235mhz 604e and UltraCache... Anyway...

When I boot it chimes but the screen just stays black. Cuda reset or not, i get nothing. And this is with my PCC branded 225/45 604e card. Could it be the bus speed throwing it off?

I'm out of my depth at any rate. :) Thanks for the advice.

 
Does the machine work with the stock cache card?
Unfortunately, it came with a G3 PowerLogix CPU card and no cache installed... and I don't have a compatible cache DIMM, just the one  from my 4400.

That being said, I am trying this with the 604e/225 PCC CPU card that I got, not the G3 card.

 
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So, does anyone know if this was standard procedure? I think because it's identical it might be... but can anyone confirm by chance?

I was looking at the cache dimm to see if there were any broken traces, etc, kind of a pipe dream now, perhaps...

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You can see if you can find a datasheet for that chip and check what pins they did connect.

Might be some enable line or an unused address line that’s pulled up or down.

Nothing too unusual.

 
The cache card might be able to operate at 200mhz or whatever ("all Power Mac models" at time x) but not at 235mhz, or at 40mhz bus speed but not 50mhz, or whatever a 235mhz PowerWave runs at. It's a little like reaching the limits of hardware in overclocking. Cache cards in my experience of PCI Macs of that vintage are very sensitive to such variations, and reaching 235mhz in a 604e machine was done by the engineers pushing the hardware hard.

You could try a slower 604e, since that would presumably lower both the processor and (marginally) the bus speed in a PowerWave. It would in a Mac.

 
The cache card might be able to operate at 200mhz or whatever
I would agree with you, and I wish I could find more corroborating information about the UltraCache, specifically, which I have yet to do, but I did find this for the RapidCache, which I'll assume is a predecessor to the UltraCache in terms of product timeline, but I did find this tidbit: https://web.archive.org/web/19980504163706/http://powerlogix.com/cachemarks.html

At the very bottom is a MacBench score with a 225/45 MHz 604e, so one could assume (based on another assumption) that this product should work. I wish I could find information SPECIFICALLY about the UltraCache... :(  I'll go search MacUser archives again. 

 
This one is pretty close.  However, I'm not sure if the 36 bit wide chip just uses the NC pins for the extra 4 bits, or if the pin  out is substantially different.

Based on the pinout in the Cypress datasheet, which does show a 36 bit SRAM, the pinout is likely a JEDEC standard.   Also, the Cypress chip does use pins that are NC on the (32 bit) Galvantech part to host the final four data bits.

View attachment GVT71128D32T.pdf

View attachment CY7C1355C_CY7C1357C.pdf

 
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97 – 96

97) Chip enable: This active HIGH input is used to enable the device.

96) BW4# | BW4# controls DQ25-DQ32. Data I/O are high impedance if either of these inputs are LOW, conditioned by BWE# being LOW.

not that I know what to do with that, but that's the connection. ;)  

 
I suppose it's possible, but I find it very difficult to imagine a circumstance in which one would want the bytewise control tied to a chip enable.  If the PCI Macs supported 24 bit mode, then it might make sense (suppress the upper byte) but they don't. 

It's also a little odd that they used X36 parts.    I don't think there's any parity support on those Macs.   Maybe the price or availability was better than for the X32s at the time.

I would recommend carefully removing that solder bridge, especially if it is not on both chips.   

Just to confirm...   The PowerWave works with the 225/45 card without the cache DIMM installed?

45 MHz is on the low end of the bus speeds supported, so speed should not be an issue.   Especially since the press release says it supports up to 60MHz.   Apple only supported 40 - 50 MHz bus speeds in its PowerSurge products, but it included settings in the chip registers for speeds at least to 60.    Apple used three bits to set the motherboard bus speed (pins tied to ground on the CPU card) which implies eight set points.   Each "point" seems to encompass a 5MHz range, which gives something like a 40 MHz range of speed settings.

The PowerBoost Pro included a little microcontroller on board that adjusts those CPU card speed setting pins (CLKID_0-2) as one adjusts the bus speed, so that the CLKID pins are always set approrpriately for the chosen bus speed.    The lack of this adjustment on most upgrade cards is probably why most of them won't adjust far off of 45MHz.

I would be interested in seeing a complete scan of the cache.  Apparently, I have forty-eight of the D32-5Is in the attic.   It might be possible to manufacture copies.

 
I would recommend carefully removing that solder bridge, especially if it is not on both chips.   

Just to confirm...   The PowerWave works with the 225/45 card without the cache DIMM installed?
It is on both chips—sorry if the photos looked too identical or if I didn't call it out, but they were of each chip on the DIMM. So carefully remove the bridge there? Also, no need to try to bridge the pins to the surface connections? (please say 'no need' ;)  )

And yes, without the DIMM, the PowerWave works just fine without the DIMM installed. IIRC, the original 604/120 card was also set a 45 MHz bus.

If you're interested, I don't have the means, but I'm happy to send the DIMM your way for analysis, trag.

 
Those scores in the link given are really interesting. I had always thought that cache could give you maybe a 25% boost. Twice as fast (on some measures) with 1MB than with none is significant. 

Along those lines, 1MB cache with a slower processor is likely going to be a good deal faster than the faster 604e without cache.

I have an 8600 with a dual 180MHz 604e and 1MB cache card, both of which I have to tell you were hard to find at the time they came my way (c. 10 years ago). I could never make that 8600 run stably with a dual 200MHz 604e (which I also sourced at the same time), but it is very slick with the dual 180 and cache under OS8.6, especially in the Finder. The Finder seems to have pretty decent multithreading. The response of the machine overall is excellent, however, so given the limitations of the software elsewhere, maybe that is far more due to the cache than it is to the processor.

 
I should also note that there's a Cache Profiler driver disk, which I will happily archive if it's not somewhere already. It's more than likely required to get those higher benchmarks, but I could be wrong. 

 
Those scores in the link given are really interesting. I had always thought that cache could give you maybe a 25% boost. Twice as fast (on some measures) with 1MB than with none is significant. 

Along those lines, 1MB cache with a slower processor is likely going to be a good deal faster than the faster 604e without cache.
I don't have bench marks any more but when I went from 256 to a 1 meg cache in my 8500 the difference was huge.

I forget what I paid for the cache, $100+? but it was worth it at the time.

When I revived my 8500 a few months ago I couldn't get it to boot from the XLR8 carrier card (with a G4) so I reinstalled the original 120mhz processor without the cache and the system was painfully slow.

 
Laterally speaking, my 4400 (granted a 603e) without the cache is painfully slow. With it, it's marginally chipper for its architecture, and that's only 256k. I think motorola made 512k and 1MB cache DIMMs for all the Starmax line, but good luck finding any of those in the wild.

 
If that bridge is on both chips, I'm not sure what to tell you.   If soldering is easy for you, then I'd say, sure, give removing the bridges a try.   If it's more of a challenge then I'd avoid the risk.

The only way I can think of, that there would be a bridge like that on both chips, and that would be unwanted, is if the machinery at assembly time was making the same mistake on every instance of that package.   But that doesn't make a lot of sense to me either.   If it was a solder stencil problem, I would expect the stencil to be for the whole circuit board, not per chip.   I suppose it could have been a human error, instead.

How automated was assembly back then?   I could maybe see some kind of automated solder paste squirter that doesn't use a stencil, getting it wrong in the same place on that package because of a software bug or something.  

@MOS8_030, do you have any insight into the assembly process?   Or were you more on-chip?

Thank  you for the offer to send me the cache.  Let me put that on a back burner for a while. I would probably ohm out the connections pretty rapidly, but I'd need to set aside some time, so I don't hang on to it for too long.

Right now I'm mainly curious whether there are any components on the DIMM besides the SRAM chips.    Ignoring resistors and caps, of course.

 
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