Power Mac 7500-9600 Bus Speed Overclocking

[trag]

Excellent work, @obsolete . I don't seem to be getting notifications for new posts, for some reason. I guess 3 years isn't that long to miss a thread...

It would be interesting to build a custom cache.... Fast SRAM chips down to 2.5 ns are (or were) available... TAG RAM is always the issue, but IIRC, one can make TAG RAM with SRAM and a comparator. Need a fast Comparator though.

Another interesting possibility would be to get some of the brilliant software guys to probe HammerHead address space with the CLKID pins set to different values.

 

[obsolete]

Excellent work, @obsolete . I don't seem to be getting notifications for new posts, for some reason. I guess 3 years isn't that long to miss a thread...

Thanks @trag! I was hoping you would see this eventually. Since I posted last November, you are not even 6 months late

It would be interesting to build a custom cache.... Fast SRAM chips down to 2.5 ns are (or were) available... TAG RAM is always the issue, but IIRC, one can make TAG RAM with SRAM and a comparator. Need a fast Comparator though.

I've looked at swapping faster SRAM chips onto Apple cache DIMMs and seeing whether the TAG chips can keep up at 60MHz, but do you know whether the chips must be 5V tolerant on the I/O pins? These machines are from a weird transitional period between 5V and 3.3V. If 5V tolerance is required, that really limits the options.

I have a pair of 256KB modules that resemble D03 on @Fizzbinn's TD Wiki page: https://tinkerdifferent.com/resources/ppc-macintosh-l2-cache-modules.19/ (including the empty chip footprints on the back). One has Micron MT58LC32K32B2LG-11 chips (11ns) and the other has MT58LC32K32B2LG-9 chips (9ns). I know the -9s work up to 55MHz at least.

In the 1994 Micron SRAM Databook (warning, big PDF), MT58LC32K32B2 and MT58LC32K32C4 (and their 36-bit counterparts) specifically list "5V-tolerant I/O" as a feature. By the 1999 Micron Memory Databook, the datasheets for MT58LC32K32B4, MT58LC32K32C6, and MT58LC32K32D9 (and their 36-bit counterparts) all omit the statement about 5V tolerance. It looks like Apple used MT58LC32K32D7 on DIMM D05 on Fizzbinn's wiki page, so that might be an option.

Another interesting possibility would be to get some of the brilliant software guys to probe HammerHead address space with the CLKID pins set to different values.

Are you suggesting that the hardware CLKID straps could be overridden in software then? Or are you trying to understand which other Hammerhead register values get changed by CLKID?

 

[obsolete]

I was able to dig up a datasheet for MT58LC32K36D7 and it is in fact 5V-tolerant. That lends credence to the theory that 5V I/O compatibility is required.

 

[joevt]

Hammerhead ERS documents all the registers doesn't it?
https://tinkerdifferent.com/threads/apple-network-server-macos-based-roms-found.4756/post-41404
Write a utility to dump the values to see how the CPU slot pins affect them (if it does at all)?
Use DingusPPC emulator to follow the ExceptionTable and HWInit code during boot?
The RAM test code is commented in Diagnostics.s.
https://68kmla.org/bb/threads/skipping-the-startup-memory-test.50699/post-571099

 

[trag]

but do you know whether the chips must be 5V tolerant on the I/O pins?

I expect so. I think the way it ends up working is that the host sends 5V level signals and the chips must tolerate that. The chips send back 3.3V level signals, but the "high" logic level is high enough to register as high to the 5V logic.

Are you suggesting that the hardware CLKID straps could be overridden in software then? Or are you trying to understand which other Hammerhead register values get changed by CLKID?

Both. But I don't know. The NewerTech hardware guy said he had a utility for adjusting timing by changing Hammerhead register values, plural. Suggests more than one set of values and that it was by writing registers in Hammerhead. But I'm making a lot of stew out of one potato.

 

[trag]

Hammerhead ERS documents all the registers doesn't it?
https://tinkerdifferent.com/threads/apple-network-server-macos-based-roms-found.4756/post-41404

Thankyou. I've been wanting that documentation for something like 20 years. Any idea how it found it's way into the wild, and are the other documents listed as "further reading" available? Now going down a rabbit hole....

Already seeing that Hammerhead does indeed have 5 Bus Grant/Request/DBG lines available, suggesting possibility of connecting four Bandits, unless some of those are needed for the memory data path controllers. Need to check schematic.

The ANS Developer Note, as just a sort of aside, mentions the possibility of up to four Bandits in the architecture.

The problem I see is where would Interrupts (handled by Grand Central) come from for the additional slots, and, of course, the Mac ROM would need to be made aware of the additional slots, I think.

Given that Bandit and its arbiter are demonstrated on ANS to support at least 6 PCI devices, this suggests that one could go crazy and build a machine with 24 PCI slots. I'm not sure why you would want to, but maybe it could be done.