Excellent work,
@obsolete . I don't seem to be getting notifications for new posts, for some reason. I guess 3 years isn't that long to miss a thread...
Thanks
@trag! I was hoping you would see this eventually. Since I posted last November, you are not even 6 months late
It would be interesting to build a custom cache.... Fast SRAM chips down to 2.5 ns are (or were) available... TAG RAM is always the issue, but IIRC, one can make TAG RAM with SRAM and a comparator. Need a fast Comparator though.
I've looked at swapping faster SRAM chips onto Apple cache DIMMs and seeing whether the TAG chips can keep up at 60MHz, but do you know whether the chips must be 5V tolerant on the I/O pins? These machines are from a weird transitional period between 5V and 3.3V. If 5V tolerance is required, that really limits the options.
I have a pair of 256KB modules that resemble D03 on
@Fizzbinn's TD Wiki page:
https://tinkerdifferent.com/resources/ppc-macintosh-l2-cache-modules.19/ (including the empty chip footprints on the back). One has Micron MT58LC32K32B2LG-11 chips (11ns) and the other has MT58LC32K32B2LG-9 chips (9ns). I know the -9s work up to 55MHz at least.
In the
1994 Micron SRAM Databook (warning, big PDF), MT58LC32K32
B2 and MT58LC32K32
C4 (and their 36-bit counterparts) specifically list "5V-tolerant I/O" as a feature. By the
1999 Micron Memory Databook, the datasheets for MT58LC32K32
B4, MT58LC32K32
C6, and
MT58LC32K32
D9 (and their 36-bit counterparts) all omit the statement about 5V tolerance. It looks like Apple used MT58LC32K32
D7 on DIMM D05 on Fizzbinn's wiki page, so that might be an option.
Another interesting possibility would be to get some of the brilliant software guys to probe HammerHead address space with the CLKID pins set to different values.
Are you suggesting that the hardware CLKID straps could be overridden in software then? Or are you trying to understand which other Hammerhead register values get changed by CLKID?
