Looking for a logic analyzer capture on a Macintosh Portable (or M5126 backlit) motherboard, PDS connector side. I’m scoping the bus timing for a homebrew accelerator project.
Signals needed, all captured simultaneously, PDS pins in parens:
• /AS (c8)
• /DTACK (b7)
• /DELAY.CS (a5)
• /EXT.DTACK (b30) probably idle/high in stock config, but capture it anyway
• 16M reference clock (b31), just as a timebase
Trigger on falling edge of /AS. Want to see: (1) how many 16M clock cycles between /AS falling and /DTACK falling on a normal RAM access, (2) whether /DELAY.CS ever asserts during a normal cycle or only under specific conditions (e.g. slow ROM/I-O access), and (3) confirmation that /EXT.DTACK is truly unused in stock config. A few captures; one during a plain RAM read, one during a ROM read, one during any I/O access (SCC/VIA) if you can trigger on those that would be huge. 8-16 channel analyzer is plenty, all this data would be extremely helpful and valuable to me if anyone has the capability to do this.
Signals needed, all captured simultaneously, PDS pins in parens:
• /AS (c8)
• /DTACK (b7)
• /DELAY.CS (a5)
• /EXT.DTACK (b30) probably idle/high in stock config, but capture it anyway
• 16M reference clock (b31), just as a timebase
Trigger on falling edge of /AS. Want to see: (1) how many 16M clock cycles between /AS falling and /DTACK falling on a normal RAM access, (2) whether /DELAY.CS ever asserts during a normal cycle or only under specific conditions (e.g. slow ROM/I-O access), and (3) confirmation that /EXT.DTACK is truly unused in stock config. A few captures; one during a plain RAM read, one during a ROM read, one during any I/O access (SCC/VIA) if you can trigger on those that would be huge. 8-16 channel analyzer is plenty, all this data would be extremely helpful and valuable to me if anyone has the capability to do this.
