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Macintosh Portable SRAM card: Schematics available?
- Thread starter Stephen_Usher
- Start date
Yeah, A20's pretty important.. it's the one which enables everything.
I'm just seeing if I can write the code in CUPL using WinCUPL and running the simulator to test the logic. For this CUPL isn't that brain twisting.
I've started doing the simulator test, only done two lines so far (basically done a read cycle with A20 high and the other address lines low and then made A21 high). Seems useful other than the graphical glitches due to the program being so old and not fully Win10 compliant.
Oh, and it seems that IDC connectors and ribbon cable will be arriving tomorrow. I should be able to make a long cable first and have the card on the bench and connect the logic analyser to it. That's one benefit of having long connectors on that PLCC adapter!
I'm just seeing if I can write the code in CUPL using WinCUPL and running the simulator to test the logic. For this CUPL isn't that brain twisting.
I've started doing the simulator test, only done two lines so far (basically done a read cycle with A20 high and the other address lines low and then made A21 high). Seems useful other than the graphical glitches due to the program being so old and not fully Win10 compliant.
Oh, and it seems that IDC connectors and ribbon cable will be arriving tomorrow. I should be able to make a long cable first and have the card on the bench and connect the logic analyser to it. That's one benefit of having long connectors on that PLCC adapter!
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I couldn't get CUPL to run on Windows 10 at all without crashing. Futzed around for hours trying to install ancient runtime packages and nothing helped.
Last week because I'm apparently a stupid glutton for punishment I actually did get it working on WINE, it seems to work fine on that. I tested it out by translating my board's memory decoder GAL program to CUPL and succeeded in getting it to generate a .jed file, but for now I'm sticking with GALASM because I can run that anywhere and I'm not sure CUPL really adds a lot of value for a simple decoder. (It is *kind* of cool that you can set up the translation equations so you can test against human-readable addresses, but it's simple enough to just fire up a HEX to Binary calculator and sic it on your address; whether a bit position is a 1 or a 0 translates to if you /negate it or not.)
Haven't had the patience to try to figure out the simulator in CUPL yet, that's what I use my arduino binary counter setup for.
So, I've created the CUPL file, burned the GAL and done the patch wire..
The IDC connectors and ribbon cable arrived but I made the mistake of modifying the male IDC connector before trying to put it on the cable. It wouldn't clamp and broke and that was the only one I didn't get multiple of, so I've ordered some more which should arrive tomorrow.
On a positive note, the standard 50 pin connectors work. The male one has to have one side removed so as to pass the circuit board.
The IDC connectors and ribbon cable arrived but I made the mistake of modifying the male IDC connector before trying to put it on the cable. It wouldn't clamp and broke and that was the only one I didn't get multiple of, so I've ordered some more which should arrive tomorrow.
On a positive note, the standard 50 pin connectors work. The male one has to have one side removed so as to pass the circuit board.
So I guess we're even on forgetting to add traces. I was testing the last untried section of my uberboard last night, the EMS page flipper, and found it was completely fouled up. (It looked like pages were being shuffled around essentially at random. I was able to confirm this was what was actually going on by sic-ing my ancient 80's logic probe on it.) Long story short, I completely brainfarted and forgot to route /IOW to the GAL and use it as part of the enable equation for writing to the paging registers. The mistake was sort of understandable because everything else I was decoding had "chip enable" lines and separately watched the system read/write signals, the paging registers were unique in needing a single enable/write strobe, but I am still kicking myself because my initial sketches had it right. Added a jumper wire between the missing signal and an extra input on the GAL and it works, but I am disappointed; I came *this close* to getting a first-run board that needed no bodge wires. 
D-oh! Oh well.
One bodge wire doesn't look too bad.
One bodge wire doesn't look too bad.
I think I'll get away with having my bodge on the bottom where no one can see it. There's a via I can drill out to make the fix routeable on the dark side. 
When you get things so you can actually plug it in I guess we'll find out if /DELAYCS is actually a needed part of the equation. I do get a bad vibe that every manual on the Portable doesn't entirely correctly say what it's for, a suspicion bolstered by how they thought it was fine to ditch it on the backlight portable for something else.
When you get things so you can actually plug it in I guess we'll find out if /DELAYCS is actually a needed part of the equation. I do get a bad vibe that every manual on the Portable doesn't entirely correctly say what it's for, a suspicion bolstered by how they thought it was fine to ditch it on the backlight portable for something else.
I've just done a first test. No magic smoke!
However, the machine doesn't even start to boot. The floppy twitches once as usual and then the display comes on with random garbage but that's it.
I'll have to get the logic analyser out.
P.S. Swapping the original chip with my PCB reverted the symptoms to the original, which is good as it shows that the socket is fine and it must be an issue with my board.
However, the machine doesn't even start to boot. The floppy twitches once as usual and then the display comes on with random garbage but that's it.
I'll have to get the logic analyser out.
P.S. Swapping the original chip with my PCB reverted the symptoms to the original, which is good as it shows that the socket is fine and it must be an issue with my board.
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It's got to be my GAL programming:
No GAL: system boots.
Blank GAL: system boots.
Programmed GAL with A20 connected: hang.
Programmed GAL with A20 disconnected: hang.
This suggests the logic for the 245 is wrong as obviously the system data lines are being corrupted. Definitely time for the logic probe, but that'll probably have to wait until tomorrow.
Oh, and /DELAY_CS is always low (though very noisy)
P.S. Doh! I'd forgotten to program the 245OE at all. That's done. The machine boots but only sees 1MB of RAM. More investigation necessary, with a logic probe to see what addresses the system is looking for for the RAM and to see if I've made more mistakes with the GAL programming,
No GAL: system boots.
Blank GAL: system boots.
Programmed GAL with A20 connected: hang.
Programmed GAL with A20 disconnected: hang.
This suggests the logic for the 245 is wrong as obviously the system data lines are being corrupted. Definitely time for the logic probe, but that'll probably have to wait until tomorrow.
Oh, and /DELAY_CS is always low (though very noisy)
P.S. Doh! I'd forgotten to program the 245OE at all. That's done. The machine boots but only sees 1MB of RAM. More investigation necessary, with a logic probe to see what addresses the system is looking for for the RAM and to see if I've made more mistakes with the GAL programming,
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P.P.S. Of course, /DELAY_CS was causing the device to be disabled, so no wonder it wasn't seeing the RAM. So, I've changed the GAL programming to ignore /DELAY_CS and I think it may be seeing the RAM now but it gets to a certain part of the boot process (loading System 6) and then crashes with "Address Error" and the machine freezes quite quickly after that even when I go into the debugger.
I don't s'pose anyone knows of a floppy bootable RAM tester for classic Macs which doesn't need to boot the whole OS?
I don't s'pose anyone knows of a floppy bootable RAM tester for classic Macs which doesn't need to boot the whole OS?
Deleted erroneous result... Bad JED file.
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Oh, the GAL's /RAM_OE line seems to be glitching, according the logic analyser.
As you can see it's sometimes logic '1' when /154_OE is logic '0' which it should never be able as they share one of their enabling conditions. It's almost as if it needs a pull-up resistor.
You should never give the RAM both write enable and output enable at the same time.
As you can see it's sometimes logic '1' when /154_OE is logic '0' which it should never be able as they share one of their enabling conditions. It's almost as if it needs a pull-up resistor.
You should never give the RAM both write enable and output enable at the same time.
Also, Osmond PCB is now donation ware and there are versions for intel OSX, PPC OSX and PPC Classic. I like Osmond, but it's what I started out with.
https://www.osmondpcb.com/download.html
Re: PCBway, just took a look at their website and their pricing is a little odd. $5 for 10 boards, but $131 for 100 boards. I guess the 5 board pricing is to get you hooked?
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OK, I've stably got into the debugger. It seems as if address lines A15 and A16 aren't working, so I'm going to have to check the soldering again.
(0x100000 is duplicated at 0x108000 and 0x110000 but not at 0x120000)
A15 goes to one of the 74AC240s and A16 to the new board.
(0x100000 is duplicated at 0x108000 and 0x110000 but not at 0x120000)
A15 goes to one of the 74AC240s and A16 to the new board.
The original code I wrote only enables OE and WE based on the opposite state of the RW output lines from the bus:
There shouldn't be any circumstance under which it would enable both at once unless there's some internal delay in play here since RAMOE is dependent on the feedback from MEMCS. (/MEMCS would be the equiv of your /154_OE.) The weird thing is if it *was* glitching on a feedback delay it should also be glitching on all the other lines that depend on it. (745OE and the two WE lines.) Your code looks like a pretty straight translation of mine other than it looks like we reversed the required state for AS. (Maybe I had it backwards, always possible.)...
Actually, wait. I see that you're not bothering to test to see if the /UDS or /LDS lines are low before enabling OE. Is it possible that "RW" isn't stable if neither UDS or LDS is selected? (My code enables if either is low because enabling if both were high would be weird; that'd be the CPU asking to read memory from neither 8-bit bank.)
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There's a number of weird things about PCBWay's pricing model. Their 10 for $5 is a helluva deal as long as your prototype is under 100mm in any dimension, but the pricing takes a huge leap if you exceed that. My most recent project was 100x150 mm and five boards from PCBway at that size gets quoted at $34. JLCPCB was only $9.10 for five so I gave them a try this time and so far their boards seem to be of roughly equivalent quality.
I do think both companies are *really* hoping to bait you into using their manufacturing services. I'd be tempted because the prices for whole items don't really seem to be that bad, but their in-house parts catalog seems to be kind of thin when it comes to 5v legacy compatible devices.
I can tweak the GAL code. Actually I've been thinking about cleaning it up a bit anyway.
I think the thing is almost working. It looks like a may have a broken trace connecting the A15 line with the 240 inverter, so that might be an easy fix. I've not looked too far at the A16 issue other than noting that the signal is getting as far as my board.
I think the thing is almost working. It looks like a may have a broken trace connecting the A15 line with the 240 inverter, so that might be an easy fix. I've not looked too far at the A16 issue other than noting that the signal is getting as far as my board.
A couple of bad solder joints fixed and...
A slight bodge required to get it to fit in the case, using a bus extension cable... But it fits securely.
